Written by Dan Brown, Senior Manager, Content & Social Media, Linux Foundation Training & Certification
With RISC-V cores, systems-on-chips (SoCs), developer boards, and software and tools growing in adoption, there is significant need in the community for more individuals possessing skills using the RISC-V instruction set architecture (ISA). To help meet that demand, Linux Foundation Training & Certification and RISC-V International recently launched two free online training courses to reduce the barrier to entry for those interested in gaining RISC-V skills. These courses will be beneficial to the Zephyr community as the RTOS is a popular choice for developing embedded applications on RISC-V.
The first course, Introduction to RISC-V (LFD110x), guides participants through the various aspects of understanding the RISC-V ecosystem, RISC-V International, the RISC-V specifications, how to curate and develop RISC-V specifications, and the technical aspects of working with RISC-V both as a developer and end-user. The course provides the foundational knowledge needed to effectively engage in the RISC-V community, contribute to the ISA specifications, and develop a wide range of RISC-V software and hardware projects. Introduction to RISC-V was developed by Jeffrey “Jefro” Osier-Mixon, program manager for RISC-V International, and Stephano Cetola, technical program manager for RISC-V International.
The second course, Building a RISC-V CPU Core (LFD111x), focuses on digital logic design and basic central processing unit (CPU) microarchitecture. Using the Makerchip online integrated development environment (IDE), participants will implement technologies ranging from logic gates to a simple and complete RISC-V CPU core. The class will allow participants to familiarize themselves with a variety of emerging technologies supporting an open source hardware ecosystem, including RISC-V, transaction-level verilog, and the online Makerchip IDE. Building a RISC-V CPU Core was developed by Steve Hoover, founder of Redwood EDA.
Enrollment is now open for Introduction to RISC-V and Building a RISC-V CPU Core. Auditing each course through edX is free for seven weeks, or you can opt for a paid verified certificate of completion, which provides access to the course for a full year and additional assessments and content to deepen their learning experience.
RISC-V recently joined the Zephyr Project. Learn more here.