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CONFIG_CLOCK_STM32_PLL_M_DIVISOR
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PLL divisor, allowed values: 1-8. With this ensure that the PLL VCO input frequency ranges from 4 to 16MHz.
Symbol: | CLOCK_STM32_PLL_M_DIVISOR |
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Type: | int |
Value: | “1” |
User value: | (no user value) |
Visibility: | “n” |
Is choice item: | false |
Is defined: | true |
Is from env.: | false |
Is special: | false |
Ranges: |
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Prompts: |
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Default values: |
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Selects: | (no selects) |
Reverse (select-related) dependencies: | |
(no reverse dependencies) |
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Additional dependencies from enclosing menus and ifs: | |
SOC_FAMILY_STM32 && CLOCK_CONTROL && SOC_SERIES_STM32L4X (value: “n”) |
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Locations: |
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