Configuration Options Reference Guide¶

Introduction¶

Kconfig files describe the configuration symbols supported in the build system, the logical organization and structure that group the symbols in menus and sub-menus, and the relationships between the different configuration symbols that govern the valid configuration combinations.

The Kconfig files are distributed across the build directory tree. The files are organized based on their common characteristics and on what new symbols they add to the configuration menus.

The configuration options’ information is extracted directly from Kconfig using the ~/doc/scripts/genrest/genrest.py script.

Supported Options¶

Configuration Options¶
`CONFIG_KERNELVERSION`
`CONFIG_ARC`	ARC architecture
`CONFIG_ARM`	ARM architecture
`CONFIG_X86`	x86 architecture
`CONFIG_NIOS2`	Nios II Gen 2 architecture
`CONFIG_RISCV32`	RISCV32 architecture
`CONFIG_XTENSA`	Xtensa architecture
`CONFIG_SYS_POWER_LOW_POWER_STATE_SUPPORTED`
`CONFIG_SYS_POWER_DEEP_SLEEP_SUPPORTED`
`CONFIG_BOOTLOADER_CONTEXT_RESTORE_SUPPORTED`
`CONFIG_SIMPLE_FATAL_ERROR_HANDLER`	Simple system fatal error handler
`CONFIG_ARCH`
`CONFIG_SOC`
`CONFIG_SOC_SERIES`
`CONFIG_SOC_FAMILY`
`CONFIG_BOARD`
`CONFIG_GEN_ISR_TABLES`	Use generated IRQ tables
`CONFIG_GEN_IRQ_VECTOR_TABLE`	Generate an interrupt vector table
`CONFIG_GEN_SW_ISR_TABLE`	Generate a software ISR table
`CONFIG_GEN_IRQ_START_VECTOR`
`CONFIG_SOC_RISCV32_PULPINO`	Pulpino SOC implementation
`CONFIG_SOC_RISCV32_QEMU`	riscv32_qemu SOC implementation
`CONFIG_ARCH_DEFCONFIG`
`CONFIG_INCLUDE_RESET_VECTOR`	Include Reset vector
`CONFIG_IRQ_OFFLOAD`	Enable IRQ offload
`CONFIG_RISCV_SOC_CONTEXT_SAVE`	Enable SOC-based context saving in IRQ handler
`CONFIG_RISCV_SOC_INTERRUPT_INIT`	Enable SOC-based interrupt initialization
`CONFIG_RISCV_GENERIC_TOOLCHAIN`	Compile using generic riscv32 toolchain
`CONFIG_RISCV_HAS_CPU_IDLE`	Does SOC has CPU IDLE instruction
`CONFIG_SOC_ATOM`	Intel ATOM SoC
`CONFIG_SOC_IA32`	Generic IA32 SoC
`CONFIG_SOC_SERIES_QUARK_D2000`	Quark D2000 Series MCU
`CONFIG_SOC_SERIES_QUARK_SE`	Quark SE Series MCU
`CONFIG_SOC_SERIES_QUARK_X1000`	Intel Quark X1000 Series
`CONFIG_NESTED_INTERRUPTS`	Enable nested interrupts
`CONFIG_EXCEPTION_DEBUG`	Unhandled exception debugging
`CONFIG_IDT_NUM_VECTORS`	Number of IDT vectors
`CONFIG_MAX_IRQ_LINES`	Number of IRQ lines
`CONFIG_PHYS_LOAD_ADDR`	Physical load address
`CONFIG_PHYS_RAM_ADDR`	Physical RAM address
`CONFIG_RAM_SIZE`	Amount of RAM given to the kernel (in kB)
`CONFIG_ROM_SIZE`	Amount of ROM given to the kernel (in kB)
`CONFIG_SET_GDT`	Setup GDT as part of boot process
`CONFIG_GDT_DYNAMIC`	Store GDT in RAM so that it can be modified
`CONFIG_DEBUG_IRQS`	Extra interrupt debugging functionality
`CONFIG_CPU_ATOM`
`CONFIG_CPU_MINUTEIA`
`CONFIG_CPU_HAS_FPU`
`CONFIG_X86_IAMCU`	IAMCU calling convention
`CONFIG_FLOAT`	Floating point registers
`CONFIG_FP_SHARING`	Floating point register sharing
`CONFIG_SSE`	SSE registers
`CONFIG_SSE_FP_MATH`	Compiler-generated SSEx instructions
`CONFIG_REBOOT_RST_CNT`	Reboot via RST_CNT register
`CONFIG_ISA_IA32`
`CONFIG_IA32_LEGACY_IO_PORTS`	Support IA32 legacy IO ports
`CONFIG_CMOV`
`CONFIG_CACHE_LINE_SIZE_DETECT`	Detect cache line size at runtime
`CONFIG_CACHE_LINE_SIZE`	Cache line size
`CONFIG_CLFLUSH_INSTRUCTION_SUPPORTED`	CLFLUSH instruction supported
`CONFIG_CLFLUSH_DETECT`	Detect support of CLFLUSH instruction at runtime
`CONFIG_ARCH_CACHE_FLUSH_DETECT`
`CONFIG_CACHE_FLUSHING`	Enable cache flushing mechanism
`CONFIG_PIC_DISABLE`	Disable PIC
`CONFIG_IRQ_OFFLOAD_VECTOR`	IDT vector to use for IRQ offload
`CONFIG_XIP`	Execute in place
`CONFIG_X86_FIXED_IRQ_MAPPING`
`CONFIG_SOC_FAMILY_QUARK`
`CONFIG_SOC_QUARK_D2000`	Intel Quark D2000
`CONFIG_SOC_QUARK_SE_C1000`	Intel Quark SE C1000
`CONFIG_SOC_QUARK_SE_CURIE`	Intel Curie
`CONFIG_SOC_QUARK_X1000`	Quark X1000
`CONFIG_BSP_SHARED_GDT_RAM_ADDR`	Address of the shared RAM with the QMSI Bootloader
`CONFIG_BSP_SHARED_GDT_RAM_SIZE`	Size of the shared RAM with the QMSI Bootloader
`CONFIG_EOI_FORWARDING_BUG`
`CONFIG_SS_RESET_VECTOR`	Sensor Subsystem Reset Vector
`CONFIG_ARC_INIT`	Quark SE ARC Kickoff
`CONFIG_SYS_LOG_ARC_INIT_LEVEL`	Quark SE Sensor Subsystem log level
`CONFIG_ARC_GDB_ENABLE`	Allows the usage of GDB with the ARC processor.
`CONFIG_QUARK_SE_IPM_IRQ_PRI`	IPM interrupt priority
`CONFIG_QUARK_SE_IPM_CONSOLE_RING_BUF_SIZE32`	IPM Console Ring Buffer Size
`CONFIG_BSP_SHARED_RESTORE_INFO_RAM_ADDR`	Address of the restore information in RAM shared with the QMSI Bootloader
`CONFIG_BSP_SHARED_RESTORE_INFO_SIZE`	Size of the restore information in RAM shared with the QMSI Bootloader
`CONFIG_cpsw4irq`	cpsw4irq core
`CONFIG_sample_controller`	sample_controller core
`CONFIG_sample_flix`	sample_flix core
`CONFIG_hifi3_bd5`	hifi3_bd5 core
`CONFIG_hifi3_bd5_call0`	hifi3_bd5_call0 (hifi3_bd5 core with call0 ABI and 3 additional SW IRQs)
`CONFIG_tie_dev2`	tie_dev2 core
`CONFIG_XRC_FUSION_AON_ALL_LM`	XRC_FUSION_AON_ALL_LM core
`CONFIG_tie_dev1`	tie_dev1 core
`CONFIG_sample_config`	sample_config core
`CONFIG_hifiep_bd5`	hifiep_bd5 core
`CONFIG_D_108mini`	D_108mini core
`CONFIG_D_212GP`	D_212GP core
`CONFIG_D_233L`	D_233L core
`CONFIG_hifi_mini`	hifi_mini core
`CONFIG_hifi_mini_4swIrq`	hifi_mini_4swIrq (hifi_mini core with 4 additional SW IRQs)
`CONFIG_hifi2_std`	hifi2_std core
`CONFIG_XRC_D2PM`	XRC_D2PM core
`CONFIG_XRC_D2PM_5swIrq`	XRC_D2PM_5swIrq (XRC_D2PM core with 4 additional SW IRQs)
`CONFIG_hifi4_bd7`	hifi4_bd7 core
`CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC`	Hardware clock cycles per second, 2000000 for ISS
`CONFIG_XTENSA_NO_IPC`	Core has no IPC support
`CONFIG_SW_ISR_TABLE`	Enable software interrupt handler table
`CONFIG_SW_ISR_TABLE_DYNAMIC`	Allow installing interrupt handlers at runtime
`CONFIG_IRQ_OFFLOAD_INTNUM`	IRQ offload SW interrupt index
`CONFIG_SOC_NIOS2_QEMU`	Nios II - Experimental QEMU emulation
`CONFIG_SOC_NIOS2F_ZEPHYR`	Nios IIf - Zephyr Golden Configuration
`CONFIG_CPU_NIOS2_GEN2`
`CONFIG_NUM_IRQS`	Upper limit of interrupt numbers/IDs used
`CONFIG_HAS_MUL_INSTRUCTION`
`CONFIG_HAS_DIV_INSTRUCTION`
`CONFIG_HAS_MULX_INSTRUCTION`
`CONFIG_EXTRA_EXCEPTION_INFO`	Extra exception debug information
`CONFIG_GP_NONE`	No global pointer
`CONFIG_GP_LOCAL`	Local data global pointer references
`CONFIG_GP_GLOBAL`	Global data global pointer references
`CONFIG_GP_ALL_DATA`	All data global pointer references
`CONFIG_SOC_SERIES_SAME70`	Atmel SAME70 MCU
`CONFIG_SOC_SERIES_KINETIS_K6X`	Kinetis K6x Series MCU
`CONFIG_SOC_SERIES_KINETIS_KWX`	Kinetis KWx Series MCU
`CONFIG_SOC_SERIES_CC32XX`	TI SimpleLink Family
`CONFIG_SOC_SERIES_BEETLE`	ARM Beetle MCU Series
`CONFIG_SOC_SERIES_MPS2`	ARM MPS2 MCU Series
`CONFIG_SOC_SERIES_STM32L4X`	STM32L4x Series MCU
`CONFIG_SOC_SERIES_STM32F1X`	STM32F1x Series MCU
`CONFIG_SOC_SERIES_STM32F3X`	STM32F3x Series MCU
`CONFIG_SOC_SERIES_STM32F4X`	STM32F4x Series MCU
`CONFIG_SOC_ATMEL_SAM3X8E`	Atmel SAM3X8E Processor
`CONFIG_SOC_SERIES_NRF52X`	Nordic Semiconductor nRF52 series MCU
`CONFIG_SOC_SERIES_NRF51X`	Nordic Semiconductor nRF51 series MCU
`CONFIG_SOC_TI_LM3S6965`	TI LM3S6965
`CONFIG_CPU_CORTEX`
`CONFIG_CPU_CORTEX_M`
`CONFIG_CPU_HAS_SYSTICK`
`CONFIG_FP_HARDABI`	Floating point Hard ABI
`CONFIG_FP_SOFTABI`	Floating point Soft ABI
`CONFIG_ISA_THUMB2`
`CONFIG_CPU_CORTEX_M_HAS_BASEPRI`
`CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS`
`CONFIG_ARMV6_M`
`CONFIG_ARMV7_M`
`CONFIG_CPU_CORTEX_M0`
`CONFIG_CPU_CORTEX_M0PLUS`
`CONFIG_CPU_CORTEX_M3`
`CONFIG_CPU_CORTEX_M4`
`CONFIG_CPU_CORTEX_M7`
`CONFIG_LDREX_STREX_AVAILABLE`
`CONFIG_DATA_ENDIANNESS_LITTLE`
`CONFIG_STACK_ALIGN_DOUBLE_WORD`	Align stacks on double-words (8 octets)
`CONFIG_NUM_IRQ_PRIO_BITS`
`CONFIG_RUNTIME_NMI`	Attach an NMI handler at runtime
`CONFIG_FAULT_DUMP`	Fault dump level
`CONFIG_SRAM_SIZE`	SRAM Size in kB
`CONFIG_SRAM_BASE_ADDRESS`	SRAM Base Address
`CONFIG_FLASH_SIZE`	Flash Size in kB
`CONFIG_FLASH_BASE_ADDRESS`	Flash Base Address
`CONFIG_ZERO_LATENCY_IRQS`	Enable zero-latency interrupts
`CONFIG_ARCH_HAS_THREAD_ABORT`
`CONFIG_SOC_PART_NUMBER_SAME70Q21`	SAME70Q21
`CONFIG_SOC_PART_NUMBER_SAME70Q20`	SAME70Q20
`CONFIG_SOC_PART_NUMBER_SAME70Q19`	SAME70Q19
`CONFIG_SOC_PART_NUMBER_SAME70N21`	SAME70N21
`CONFIG_SOC_PART_NUMBER_SAME70N20`	SAME70N20
`CONFIG_SOC_PART_NUMBER_SAME70N19`	SAME70N19
`CONFIG_SOC_PART_NUMBER_SAME70J21`	SAME70J21
`CONFIG_SOC_PART_NUMBER_SAME70J20`	SAME70J20
`CONFIG_SOC_PART_NUMBER_SAME70J19`	SAME70J19
`CONFIG_SOC_ATMEL_SAME70_EXT_SLCK`	Use external crystal oscillator for slow clock
`CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK`	Use external crystal oscillator for main clock
`CONFIG_SOC_ATMEL_SAME70_MDIV`	MDIV
`CONFIG_SOC_ATMEL_SAME70_PLLA_MULA`	PLL MULA
`CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA`	PLL DIVA
`CONFIG_SOC_ATMEL_SAME70_WAIT_MODE`	Go to Wait mode instead of Sleep mode
`CONFIG_SOC_ATMEL_SAME70_DISABLE_ERASE_PIN`	Disable ERASE pin
`CONFIG_SOC_FAMILY_KINETIS`
`CONFIG_SOC_MK64F12`	SOC_MK64F12
`CONFIG_SOC_PART_NUMBER_MK64FN1M0CAJ12`
`CONFIG_SOC_PART_NUMBER_MK64FN1M0VDC12`
`CONFIG_SOC_PART_NUMBER_MK64FN1M0VLL12`
`CONFIG_SOC_PART_NUMBER_MK64FN1M0VLQ12`
`CONFIG_SOC_PART_NUMBER_MK64FN1M0VMD12`
`CONFIG_SOC_PART_NUMBER_MK64FX512VDC12`
`CONFIG_SOC_PART_NUMBER_MK64FX512VLL12`
`CONFIG_SOC_PART_NUMBER_MK64FX512VLQ12`
`CONFIG_SOC_PART_NUMBER_MK64FX512VMD12`
`CONFIG_SOC_PART_NUMBER_KINETIS_K6X`
`CONFIG_K64_CORE_CLOCK_DIVIDER`	Freescale K64 core clock divider
`CONFIG_K64_BUS_CLOCK_DIVIDER`	Freescale K64 bus clock divider
`CONFIG_K64_FLEXBUS_CLOCK_DIVIDER`	Freescale K64 FlexBus clock divider
`CONFIG_K64_FLASH_CLOCK_DIVIDER`	Freescale K64 flash clock divider
`CONFIG_WDOG_INIT`
`CONFIG_PRESERVE_JTAG_IO_PINS`	Kinetis K6x JTAG pin usage
`CONFIG_SOC_MKW41Z4`	SOC_MKW41Z4
`CONFIG_SOC_PART_NUMBER_MKW41Z256VHT4`
`CONFIG_SOC_PART_NUMBER_MKW41Z512VHT4`
`CONFIG_SOC_PART_NUMBER_KINETIS_KWX`
`CONFIG_SOC_PART_NUMBER`
`CONFIG_HAS_OSC`
`CONFIG_HAS_MCG`
`CONFIG_HAS_RNGA`
`CONFIG_HAS_LPUART`
`CONFIG_OSC_EXTERNAL`	External reference clock
`CONFIG_OSC_LOW_POWER`	Low power oscillator
`CONFIG_OSC_HIGH_GAIN`	High gain oscillator
`CONFIG_OSC_XTAL0_FREQ`	External oscillator frequency
`CONFIG_MCG_PRDIV0`	PLL external reference divider
`CONFIG_MCG_VDIV0`	VCO 0 divider
`CONFIG_MCG_FCRDIV`	Fast internal reference clock divider
`CONFIG_MCG_FRDIV`	FLL external reference divider
`CONFIG_SOC_FAMILY_TISIMPLELINK`
`CONFIG_SOC_CC3200`	CC3200
`CONFIG_SOC_FAMILY_ARM`
`CONFIG_SOC_BEETLE_R0`	ARM BEETLE R0
`CONFIG_SOC_MPS2_AN385`	ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)
`CONFIG_SOC_FAMILY_STM32`
`CONFIG_SOC_STM32L476XX`	STM32L476XX
`CONFIG_SOC_STM32F103XE`	STM32F103XE
`CONFIG_SOC_STM32F103XB`	STM32F103XB
`CONFIG_SOC_STM32F107XC`	STM32F107XC
`CONFIG_SOC_STM32F10X_DENSITY_DEVICE`
`CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE`
`CONFIG_SOC_STM32F303XC`	STM32F303XC
`CONFIG_SOC_STM32F334X8`	STM32F334X8
`CONFIG_SOC_STM32F373XC`	STM32F373XC
`CONFIG_SOC_STM32F401XE`	STM32F401XE
`CONFIG_SOC_STM32F411XE`	STM32F411XE
`CONFIG_SOC_ATMEL_SAM3`
`CONFIG_SOC_ATMEL_SAM3_EXT_SLCK`	Atmel SAM3 to use external crystal oscillator for slow clock
`CONFIG_SOC_ATMEL_SAM3_EXT_MAINCK`	Atmel SAM3 to use external crystal oscillator for main clock
`CONFIG_SOC_ATMEL_SAM3_PLLA_MULA`
`CONFIG_SOC_ATMEL_SAM3_PLLA_DIVA`
`CONFIG_SOC_ATMEL_SAM3_WAIT_MODE`	Atmel SAM3 goes to Wait mode instead of Sleep mode
`CONFIG_SOC_FAMILY_NRF5`
`CONFIG_SOC_NRF52832`	NRF52832
`CONFIG_SOC_NRF52840`	NRF52840
`CONFIG_SOC_NRF51822_QFAA`	NRF51822_QFAA
`CONFIG_SOC_NRF51822_QFAB`	NRF51822_QFAB
`CONFIG_SOC_NRF51822_QFAC`	NRF51822_QFAC
`CONFIG_SOC_TI_LM3S6965_QEMU`
`CONFIG_SOC_EM11D`	Synopsys ARC EM11D
`CONFIG_SOC_QUARK_SE_C1000_SS`	Intel Quark SE C1000- Sensor Sub System
`CONFIG_SOC_EM7D`	Synopsys ARC EM7D
`CONFIG_SOC_EM9D`	Synopsys ARC EM9D
`CONFIG_CPU_ARCEM4`
`CONFIG_CPU_ARCV2`
`CONFIG_NSIM`	Running on the MetaWare nSIM simulator
`CONFIG_NUM_IRQ_PRIO_LEVELS`	Number of supported interrupt priority levels
`CONFIG_RGF_NUM_BANKS`	Number of General Purpose Register Banks
`CONFIG_FIRQ_STACK_SIZE`	Size of stack for FIRQs (in bytes)
`CONFIG_ARC_STACK_CHECKING`	Enable Stack Checking
`CONFIG_HARVARD`	Harvard Architecture
`CONFIG_ICCM_SIZE`	ICCM Size in kB
`CONFIG_ICCM_BASE_ADDRESS`	ICCM Base Address
`CONFIG_DCCM_SIZE`	DCCM Size in kB
`CONFIG_DCCM_BASE_ADDRESS`	DCCM Base Address
`CONFIG_QUARK_SE_SS_IPM_IRQ_PRI`	IPM interrupt priority
`CONFIG_BOARD_DEPRECATED`
`CONFIG_BOARD_ZEDBOARD_PULPINO`	Zedboard pulpino target
`CONFIG_BOARD_QEMU_RISCV32`	QEMU RISCV32 target
`CONFIG_BOARD_PANTHER`	Panther
`CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD`	Quark SE C1000 Devboard
`CONFIG_BOARD_TINYTILE`	TinyTILE
`CONFIG_BOARD_ARDUINO_101`	Arduino 101 Board
`CONFIG_BOARD_QUARK_D2000_CRB`	Intel Quark D2000 CRB
`CONFIG_BOARD_MINNOWBOARD`	Minnowboard Max
`CONFIG_BOARD_GALILEO`	Galileo Gen2
`CONFIG_BOARD_QEMU_X86`	QEMU x86
`CONFIG_SIMULATOR_XTENSA`	Xtensa Development ISS
`CONFIG_BOARD_QEMU_NIOS2`	QEMU NIOS II target
`CONFIG_BOARD_ALTERA_MAX10`	Altera MAX10 Board
`CONFIG_BOARD_NRF51_PCA10028`	nRF51 PCA10028
`CONFIG_BOARD_ARDUINO_DUE`	Arduino Due Board
`CONFIG_BOARD_NUCLEO_F411RE`	NUCLEO-64 F411RE Development Board
`CONFIG_BOARD_V2M_BEETLE`	ARM V2M Beetle Board
`CONFIG_BOARD_STM3210C_EVAL`	STM3210C-EVAL Evaluation Board
`CONFIG_BOARD_NUCLEO_L476RG`	Nucleo L476RG Development Board
`CONFIG_BOARD_BBC_MICROBIT`	BBC MICRO:BIT
`CONFIG_BOARD_QEMU_CORTEX_M3`	Cortex-M3 Emulation (Qemu)
`CONFIG_BOARD_HEXIWEAR_K64`	NXP Hexiwear K64
`CONFIG_BOARD_ARDUINO_101_BLE`	Arduino 101 BLE
`CONFIG_BOARD_NRF51_BLENANO`	nRF51 BLENANO
`CONFIG_BOARD_NRF52_PCA10040`	nRF52 PCA10040
`CONFIG_BOARD_96B_CARBON`	96Boards Carbon (STM32F401)
`CONFIG_BOARD_SAM_E70_XPLAINED`	Atmel SMART SAM E70 Xplained Board
`CONFIG_BOARD_NUCLEO_F334R8`	NUCLEO-64 F334R8 Development Board
`CONFIG_BOARD_NRF52840_PCA10056`	NRF52840 PCA10056
`CONFIG_BOARD_NUCLEO_F401RE`	NUCLEO-64 F401RE Development Board
`CONFIG_BOARD_QUARK_SE_C1000_BLE`	Quark SE C1000 Devboard - BLE Core
`CONFIG_BOARD_OLIMEXINO_STM32`	OLIMEXINO-STM32 Development Board
`CONFIG_BOARD_FRDM_K64F`	Freescale FRDM-K64F
`CONFIG_BOARD_96B_NITROGEN`	96Boards Nitrogen
`CONFIG_BOARD_MPS2_AN385`	ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)
`CONFIG_BOARD_STM32_MINI_A15`	STM32 MINI A15 Development Board
`CONFIG_BOARD_CURIE_BLE`	Curie BLE
`CONFIG_BOARD_NUCLEO_F103RB`	NUCLEO-64 F103RB Development Board
`CONFIG_BOARD_STM32373C_EVAL`	STM32373C_EVAL Evaluation Board
`CONFIG_BOARD_FRDM_KW41Z`	NXP FRDM-KW41Z
`CONFIG_BOARD_CC3200_LAUNCHXL`	TI CC3200 LAUNCHXL
`CONFIG_BOARD_EM_STARTERKIT`	ARC EM Starter Kit
`CONFIG_BOARD_ARDUINO_101_SSS`	Arduino 101 Sensor Sub System
`CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD_SS`	Quark SE C1000 - Sensor Sub System
`CONFIG_BOARD_PANTHER_SS`	Panther - Sensor Sub System
`CONFIG_PINMUX_GALILEO_EXP0_NAME`	Name of the GPIO expander 0
`CONFIG_PINMUX_GALILEO_EXP1_NAME`	Name of the GPIO expander 1
`CONFIG_PINMUX_GALILEO_EXP2_NAME`	Name of the GPIO expander 2
`CONFIG_PINMUX_GALILEO_PWM0_NAME`	Name of the PWM LED expander 0
`CONFIG_PINMUX_GALILEO_GPIO_DW_NAME`	Name of the DesignWare GPIO
`CONFIG_PINMUX_GALILEO_GPIO_INTEL_CW_NAME`	Name of the Legacy Bridge Core Well GPIO
`CONFIG_PINMUX_GALILEO_GPIO_INTEL_RW_NAME`	Name of the Legacy Bridge Resume Well GPIO
`CONFIG_XTENSA_XTSC_INC`	Xtensa XTSC extension include file
`CONFIG_GPIO_AS_PINRESET`	GPIO as pin reset (reset button)
`CONFIG_HAS_DTS`	Uses Device Tree
`CONFIG_MULTITHREADING`	Multi-threading
`CONFIG_NUM_COOP_PRIORITIES`	Number of coop priorities
`CONFIG_NUM_PREEMPT_PRIORITIES`	Number of preemptible priorities
`CONFIG_MAIN_THREAD_PRIORITY`	Priority of initialization/main thread
`CONFIG_COOP_ENABLED`
`CONFIG_PREEMPT_ENABLED`
`CONFIG_PRIORITY_CEILING`	Priority inheritance ceiling
`CONFIG_MAIN_STACK_SIZE`	Size of stack for initialization and main thread
`CONFIG_IDLE_STACK_SIZE`	Size of stack for idle thread
`CONFIG_ISR_STACK_SIZE`	ISR and initialization stack size (in bytes)
`CONFIG_THREAD_CUSTOM_DATA`	Thread custom data
`CONFIG_NUM_DYNAMIC_TIMERS`	Number of timers available for dynamic allocation
`CONFIG_ERRNO`	Enable errno support
`CONFIG_KERNEL_DEBUG`	Kernel debugging
`CONFIG_BOOT_BANNER`	Boot banner
`CONFIG_BUILD_TIMESTAMP`	Build Timestamp
`CONFIG_INT_LATENCY_BENCHMARK`	Interrupt latency metrics [EXPERIMENTAL]
`CONFIG_THREAD_MONITOR`	Thread monitoring [EXPERIMENTAL]
`CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE`	System workqueue stack size
`CONFIG_SYSTEM_WORKQUEUE_PRIORITY`	System workqueue priority
`CONFIG_OFFLOAD_WORKQUEUE_STACK_SIZE`	Workqueue stack size for thread offload requests
`CONFIG_OFFLOAD_WORKQUEUE_PRIORITY`	Offload requests workqueue priority
`CONFIG_ATOMIC_OPERATIONS_BUILTIN`
`CONFIG_ATOMIC_OPERATIONS_CUSTOM`
`CONFIG_ATOMIC_OPERATIONS_C`
`CONFIG_TIMESLICING`	Thread time slicing
`CONFIG_TIMESLICE_SIZE`	Time slice size (in ms)
`CONFIG_TIMESLICE_PRIORITY`	Time slicing thread priority ceiling
`CONFIG_POLL`	async I/O framework
`CONFIG_SEMAPHORE_GROUPS`	Enable semaphore groups
`CONFIG_NUM_MBOX_ASYNC_MSGS`	Maximum number of in-flight asynchronous mailbox messages
`CONFIG_NUM_PIPE_ASYNC_MSGS`	Maximum number of in-flight asynchronous pipe messages
`CONFIG_MEM_POOL_SPLIT_BEFORE_DEFRAG`	Split a larger block before merging smaller blocks
`CONFIG_MEM_POOL_DEFRAG_BEFORE_SPLIT`	Merge smaller blocks before splitting a larger block
`CONFIG_MEM_POOL_SPLIT_ONLY`	Split a larger block, but never merge smaller blocks
`CONFIG_HEAP_MEM_POOL_SIZE`	Heap memory pool size (in bytes)
`CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN`
`CONFIG_SYS_CLOCK_TICKS_PER_SEC`	System tick frequency (in ticks/second)
`CONFIG_SYS_CLOCK_EXISTS`
`CONFIG_INIT_STACKS`	Initialize stack areas
`CONFIG_RING_BUFFER`	Enable ring buffers
`CONFIG_KERNEL_INIT_PRIORITY_OBJECTS`	Kernel objects initialization priority
`CONFIG_KERNEL_INIT_PRIORITY_DEFAULT`	Default init priority
`CONFIG_KERNEL_INIT_PRIORITY_DEVICE`	Default init priority for device drivers
`CONFIG_APPLICATION_INIT_PRIORITY`	Default init priority for application level drivers
`CONFIG_STACK_CANARIES`	Compiler stack canaries
`CONFIG_LEGACY_KERNEL`	Legacy Kernel Options
`CONFIG_MDEF`	Use MDEF files for statically configured kernel objects
`CONFIG_NANO_TIMEOUTS`
`CONFIG_NANO_TIMERS`
`CONFIG_KERNEL_EVENT_LOGGER`	Enable kernel event logger features
`CONFIG_KERNEL_EVENT_LOGGER_BUFFER_SIZE`	Kernel event logger buffer size
`CONFIG_KERNEL_EVENT_LOGGER_DYNAMIC`	Kernel event logger dynamic enabling
`CONFIG_KERNEL_EVENT_LOGGER_CUSTOM_TIMESTAMP`	Kernel event logger custom timestamp
`CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH`	Context switch event logging point
`CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT`	Interrupt event logging point
`CONFIG_KERNEL_EVENT_LOGGER_SLEEP`	Sleep event logging point
`CONFIG_SYS_POWER_MANAGEMENT`	Power management
`CONFIG_SYS_POWER_LOW_POWER_STATE`	Low power state
`CONFIG_SYS_POWER_DEEP_SLEEP`	Deep sleep state
`CONFIG_DEVICE_POWER_MANAGEMENT`	Device power management
`CONFIG_TICKLESS_IDLE`	Tickless idle
`CONFIG_TICKLESS_IDLE_THRESH`	Tickless idle threshold
`CONFIG_BLUETOOTH_UART`
`CONFIG_BLUETOOTH_H4`	H:4 UART
`CONFIG_BLUETOOTH_H5`	H:5 UART [EXPERIMENTAL]
`CONFIG_BLUETOOTH_SPI`	SPI HCI
`CONFIG_BLUETOOTH_NO_DRIVER`	No default HCI driver
`CONFIG_BLUETOOTH_DEBUG_HCI_DRIVER`	Bluetooth HCI driver debug
`CONFIG_BLUETOOTH_UART_ON_DEV_NAME`	Device Name of UART Device for Bluetooth
`CONFIG_BLUETOOTH_SPI_DEV_NAME`	Device Name of SPI Device for Bluetooth
`CONFIG_BLUETOOTH_HCI_RESERVE`
`CONFIG_BLUETOOTH_SPI_BLUENRG`	Enable compatibility with BlueNRG-based devices
`CONFIG_BLUETOOTH_SPI_CHIP_SELECT_DEV_NAME`	Chip Select (CS) line driver name
`CONFIG_BLUETOOTH_SPI_IRQ_DEV_NAME`	IRQ line driver name
`CONFIG_BLUETOOTH_SPI_RESET_DEV_NAME`	Reset line driver name
`CONFIG_BLUETOOTH_SPI_CHIP_SELECT_PIN`	SPI Chip Select (CS) line number
`CONFIG_BLUETOOTH_SPI_IRQ_PIN`	SPI IRQ line number
`CONFIG_BLUETOOTH_SPI_RESET_PIN`	SPI Reset line number
`CONFIG_BLUETOOTH_SPI_MAX_CLK_FREQ`	Maximum clock frequency for the HCI SPI interface
`CONFIG_NBLE`	Support for custom non-HCI nRF51 firmware [DEPRECATED]
`CONFIG_BLUETOOTH_PERIPHERAL`	Peripheral Role support
`CONFIG_BLUETOOTH_CENTRAL`	Central Role support
`CONFIG_BLUETOOTH_ATT_PREPARE_COUNT`	Number of ATT prepare write buffers
`CONFIG_BLUETOOTH_GATT_CLIENT`	GATT client support
`CONFIG_BLUETOOTH_SMP`	Security Manager Protocol support
`CONFIG_BLUETOOTH_MAX_CONN`	Maximum number of simultaneous connections
`CONFIG_BLUETOOTH_MAX_PAIRED`	Maximum number of paired devices
`CONFIG_BLUETOOTH_RX_STACK_SIZE`	Size of the receiving thread stack
`CONFIG_BLUETOOTH_DEVICE_NAME`	Bluetooth device name
`CONFIG_BLUETOOTH_DEBUG_GATT`	Bluetooth Generic Attribute Profile (GATT) debug
`CONFIG_NBLE_DEBUG_GAP`	NBLE Generic Access Profile (GAP) debug
`CONFIG_NBLE_DEBUG_CONN`	NBLE connection debug
`CONFIG_NBLE_DEBUG_RPC`	NBLE RPC debug
`CONFIG_NBLE_UART_ON_DEV_NAME`	Device Name of UART Device for Nordic BLE
`CONFIG_BLUETOOTH_NRF51_PM`	nRF51 Power Management [EXPERIMENTAL]
`CONFIG_BLUETOOTH_WAIT_NOP`	Wait for “NOP” Command Complete event during init
`CONFIG_IEEE802154`
`CONFIG_SYS_LOG_IEEE802154_DRIVER_LEVEL`	IEEE802154 driver log level
`CONFIG_IEEE802154_CC2520`	TI CC2520 Driver support
`CONFIG_IEEE802154_CC2520_RAW`	TI CC2520 Driver RAW channel
`CONFIG_IEEE802154_CC2520_DRV_NAME`	TI CC2520 Driver’s name
`CONFIG_IEEE802154_CC2520_SPI_DRV_NAME`	SPI driver’s name to use to access CC2520
`CONFIG_IEEE802154_CC2520_SPI_FREQ`	SPI system frequency
`CONFIG_IEEE802154_CC2520_SPI_SLAVE`	SPI slave linked to CC2520
`CONFIG_IEEE802154_CC2520_RX_STACK_SIZE`	Driver’s internal rx thread stack size
`CONFIG_IEEE802154_CC2520_INIT_PRIO`	CC2520 intialization priority
`CONFIG_IEEE802154_MCR20A`	NXP MCR20A Driver support
`CONFIG_IEEE802154_MCR20A_RAW`	NXP MCR20A Driver RAW channel
`CONFIG_IEEE802154_MCR20A_DRV_NAME`	NXP MCR20A Driver’s name
`CONFIG_IEEE802154_MCR20A_SPI_DRV_NAME`	SPI driver’s name to use to access MCR20A
`CONFIG_IEEE802154_MCR20A_SPI_FREQ`	SPI system frequency
`CONFIG_IEEE802154_MCR20A_SPI_SLAVE`	SPI slave linked to MCR20A
`CONFIG_MCR20A_GPIO_IRQ_B_NAME`	GPIO device used for IRQ_B output of MCR20A
`CONFIG_MCR20A_GPIO_IRQ_B_PIN`	GPIO pin connected to IRQ_B output of MCR20A
`CONFIG_MCR20A_GPIO_RESET_NAME`	GPIO device used for RESET input of MCR20A
`CONFIG_MCR20A_GPIO_RESET_PIN`	GPIO pin connected to RESET input of MCR20A
`CONFIG_MCR20A_CLK_OUT_DISABLED`	Disabled
`CONFIG_MCR20A_CLK_OUT_32MHZ`	32 MHz
`CONFIG_MCR20A_CLK_OUT_16MHZ`	16 MHz
`CONFIG_MCR20A_CLK_OUT_8MHZ`	8 MHz
`CONFIG_MCR20A_CLK_OUT_4MHZ`	4 MHz
`CONFIG_MCR20A_CLK_OUT_1MHZ`	1 MHz
`CONFIG_MCR20A_CLK_OUT_250KHZ`	250 kHz
`CONFIG_MCR20A_CLK_OUT_62500HZ`	62500 Hz
`CONFIG_MCR20A_CLK_OUT_32768HZ`	32768 Hz
`CONFIG_IEEE802154_MCR20A_RX_STACK_SIZE`	Driver’s internal rx thread stack size
`CONFIG_IEEE802154_MCR20A_INIT_PRIO`	MCR20A intialization priority
`CONFIG_IEEE802154_NRF5`	nRF52 series IEEE 802.15.4 Driver support
`CONFIG_IEEE802154_NRF5_DRV_NAME`	nRF52 IEEE 802.15.4 Driver’s name
`CONFIG_IEEE802154_NRF5_RX_STACK_SIZE`	Driver’s internal rx thread stack size
`CONFIG_IEEE802154_NRF5_INIT_PRIO`	nRF52 IEEE 802.15.4 intialization priority
`CONFIG_IEEE802154_NRF5_CCA_MODE_ED`	Energy Above Threashold
`CONFIG_IEEE802154_NRF5_CCA_MODE_CARRIER`	Carrier Seen
`CONFIG_IEEE802154_NRF5_CCA_MODE_CARRIER_AND_ED`	Energy Above Threshold AND Carrier Seen
`CONFIG_IEEE802154_NRF5_CCA_MODE_CARRIER_OR_ED`	Energy Above Threshold OR Carrier Seen
`CONFIG_IEEE802154_NRF5_CCA_ED_THRESHOLD`	nRF52 IEEE 802.15.4 CCA Energy Detection threshold
`CONFIG_IEEE802154_NRF5_CCA_CORR_THRESHOLD`	nRF52 IEEE 802.15.4 CCA Correlator threshold
`CONFIG_IEEE802154_NRF5_CCA_CORR_LIMIT`	nRF52 IEEE 802.15.4 CCA Correlator limit
`CONFIG_IEEE802154_UPIPE`	UART PIPE fake radio driver support for QEMU
`CONFIG_IEEE802154_UPIPE_DRV_NAME`	UART PIPE Driver name
`CONFIG_CONSOLE`	Console drivers
`CONFIG_CONSOLE_INPUT_MAX_LINE_LEN`	Console maximum input line length
`CONFIG_CONSOLE_HAS_DRIVER`
`CONFIG_CONSOLE_HANDLER`	Enable console input handler
`CONFIG_UART_CONSOLE`	Use UART for console
`CONFIG_UART_CONSOLE_ON_DEV_NAME`	Device Name of UART Device for UART Console
`CONFIG_UART_CONSOLE_INIT_PRIORITY`	Init priority
`CONFIG_UART_CONSOLE_DEBUG_SERVER_HOOKS`	Debug server hooks in debug console
`CONFIG_USB_UART_CONSOLE`	Use USB port for console outputs
`CONFIG_RAM_CONSOLE`	Use RAM console
`CONFIG_RAM_CONSOLE_BUFFER_SIZE`	Ram Console buffer size
`CONFIG_RTT_CONSOLE`	Use RTT console
`CONFIG_IPM_CONSOLE_SENDER`	Inter-processor Mailbox console sender
`CONFIG_IPM_CONSOLE_RECEIVER`	Inter-processor Mailbox console receiver
`CONFIG_IPM_CONSOLE_STACK_SIZE`	Stack size for IPM console receiver thread
`CONFIG_IPM_CONSOLE_INIT_PRIORITY`	IPM console init priority
`CONFIG_UART_PIPE`	Enable pipe UART driver
`CONFIG_UART_PIPE_ON_DEV_NAME`	Device Name of UART Device for pipe UART
`CONFIG_XTENSA_SIM_CONSOLE`	Use Xtensa simulator console
`CONFIG_XTENSA_CONSOLE_INIT_PRIORITY`	Init priority
`CONFIG_TELNET_CONSOLE`	Enable a super basic telnet console service
`CONFIG_TELNET_CONSOLE_PORT`	Telnet console port number
`CONFIG_TELNET_CONSOLE_LINE_BUF_SIZE`	Telnet console line buffer size
`CONFIG_TELNET_CONSOLE_LINE_BUF_NUMBERS`	Telnet console line buffers
`CONFIG_TELNET_CONSOLE_SEND_TIMEOUT`	Telnet console line send timeout
`CONFIG_TELNET_CONSOLE_SEND_THRESHOLD`	Telnet console line send threshold
`CONFIG_TELNET_CONSOLE_SUPPORT_COMMAND`	Add support for telnet commands (IAC) [Experimental]
`CONFIG_TELNET_CONSOLE_THREAD_STACK`	Telnet console inner thread stack size
`CONFIG_TELNET_CONSOLE_PRIO`	Telnet console inner thread priority
`CONFIG_SYS_LOG_TELNET_CONSOLE_LEVEL`	Telnet console log level
`CONFIG_TELNET_CONSOLE_DEBUG_DEEP`	Forward output to original console handler
`CONFIG_TELNET_CONSOLE_INIT_PRIORITY`	Telnet console init priority
`CONFIG_SYS_LOG_ETHERNET_LEVEL`	Ethernet driver log level
`CONFIG_ETH_INIT_PRIORITY`	Ethernet driver init priority
`CONFIG_ETH_ENC28J60`	ENC28J60C Ethernet Controller
`CONFIG_ETH_ENC28J60_RX_THREAD_STACK_SIZE`	Stack size for internal incoming packet handler
`CONFIG_ETH_ENC28J60_RX_THREAD_PRIO`	Priority for internal incoming packet handler
`CONFIG_ETH_ENC28J60_0`	ENC28J60C Ethernet port 0
`CONFIG_ETH_ENC28J60_0_NAME`	Driver’s name
`CONFIG_ETH_EN28J60_0_FULL_DUPLEX`	ENC28J60 full duplex
`CONFIG_ETH_ENC28J60_0_GPIO_PORT_NAME`	GPIO controller port name
`CONFIG_ETH_ENC28J60_0_GPIO_PIN`	ENC28J60C INT GPIO PIN
`CONFIG_ETH_ENC28J60_0_SPI_PORT_NAME`	SPI master controller port name
`CONFIG_ETH_ENC28J60_0_SLAVE`	ETH_ENC28J60 SPI slave select pin
`CONFIG_ETH_ENC28J60_0_SPI_BUS_FREQ`	ENC28J60C SPI bus speed in Hz
`CONFIG_ETH_ENC28J60_0_MAC3`	MAC Address Byte 3
`CONFIG_ETH_ENC28J60_0_MAC4`	MAC Address Byte 4
`CONFIG_ETH_ENC28J60_0_MAC5`	MAC Address Byte 5
`CONFIG_ETH_MCUX`	MCUX Ethernet driver
`CONFIG_ETH_MCUX_PHY_TICK_MS`	PHY poll period (ms)
`CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG`	Enable additional detailed PHY debug
`CONFIG_ETH_MCUX_RX_BUFFERS`	Number of MCUX RX buffers
`CONFIG_ETH_MCUX_TX_BUFFERS`	Number of MCUX TX buffers
`CONFIG_ETH_MCUX_0`	MCUX Ethernet port 0
`CONFIG_ETH_MCUX_0_NAME`	Driver name
`CONFIG_ETH_MCUX_0_IRQ_PRI`	Controller interrupt priority
`CONFIG_ETH_MCUX_0_RANDOM_MAC`	Random MAC address
`CONFIG_ETH_MCUX_0_MAC3`	MAC Address Byte 3
`CONFIG_ETH_MCUX_0_MAC4`	MAC Address Byte 4
`CONFIG_ETH_MCUX_0_MAC5`	MAC Address Byte 5
`CONFIG_ETH_DW`	Synopsys DesignWare Ethernet driver
`CONFIG_ETH_DW_SHARED_IRQ`
`CONFIG_ETH_DW_0`	Synopsys DesignWare Ethernet port 0
`CONFIG_ETH_DW_0_NAME`	Driver name
`CONFIG_ETH_DW_0_IRQ_DIRECT`	Direct Hardware Interrupt
`CONFIG_ETH_DW_0_IRQ_SHARED`	Shared IRQ
`CONFIG_ETH_DW_0_IRQ_SHARED_NAME`	Device name for Shared IRQ
`CONFIG_ETH_DW_0_IRQ_PRI`	Controller interrupt priority
`CONFIG_ETH_SAM_GMAC`	Atmel SAM Ethernet driver
`CONFIG_ETH_SAM_GMAC_NAME`	Device name
`CONFIG_ETH_SAM_GMAC_NBUF_DATA_COUNT`	Network data buffers pre-allocated by the SAM ETH driver
`CONFIG_ETH_SAM_GMAC_IRQ_PRI`	Interrupt priority
`CONFIG_ETH_SAM_GMAC_MAC0`	MAC Address Byte 0
`CONFIG_ETH_SAM_GMAC_MAC1`	MAC Address Byte 1
`CONFIG_ETH_SAM_GMAC_MAC2`	MAC Address Byte 2
`CONFIG_ETH_SAM_GMAC_MAC3`	MAC Address Byte 3
`CONFIG_ETH_SAM_GMAC_MAC4`	MAC Address Byte 4
`CONFIG_ETH_SAM_GMAC_MAC5`	MAC Address Byte 5
`CONFIG_ETH_SAM_GMAC_RMII`	RMII
`CONFIG_ETH_SAM_GMAC_MII`	MII
`CONFIG_ETH_SAM_GMAC_PHY_ADDR`	GMAC PHY Address
`CONFIG_SLIP`	SLIP driver
`CONFIG_SLIP_DRV_NAME`	SLIP Driver name
`CONFIG_SLIP_MTU`	SLIP MTU
`CONFIG_SLIP_DEBUG`	SLIP driver debug
`CONFIG_SLIP_STATISTICS`	SLIP network connection statistics
`CONFIG_SLIP_TAP`	Use TAP interface to host
`CONFIG_SERIAL`	Serial Drivers
`CONFIG_SERIAL_HAS_DRIVER`
`CONFIG_UART_INTERRUPT_DRIVEN`	Enable UART Interrupt support
`CONFIG_UART_LINE_CTRL`	Enable Serial Line Control API
`CONFIG_UART_DRV_CMD`	Enable driver commands API
`CONFIG_UART_NS16550`	NS16550 serial driver
`CONFIG_UART_NS16550_PCI`	Enable PCI Support
`CONFIG_UART_NS16550_DLF`	Enable Divisor Latch Fraction (DLF) support
`CONFIG_UART_NS16550_LINE_CTRL`	Enable Serial Line Control for Apps
`CONFIG_UART_NS16550_DRV_CMD`	Enable Driver Commands
`CONFIG_UART_NS16750`	Enable 64-bytes FIFO for UART 16750
`CONFIG_UART_NS16550_PORT_0`	Enable NS16550 Port 0
`CONFIG_UART_NS16550_PORT_0_NAME`	Port 0 Device Name
`CONFIG_UART_NS16550_PORT_0_IRQ_PRI`	Port 0 Interrupt Priority
`CONFIG_UART_NS16550_PORT_0_BAUD_RATE`	Port 0 Baud Rate
`CONFIG_UART_NS16550_PORT_0_OPTIONS`	Port 0 Options
`CONFIG_UART_NS16550_PORT_0_DLF`	Port 0 DLF value
`CONFIG_UART_NS16550_PORT_0_PCI`	Port 0 is PCI-based
`CONFIG_UART_NS16550_PORT_1`	Enable NS16550 Port 1
`CONFIG_UART_NS16550_PORT_1_NAME`	Port 1 Device Name
`CONFIG_UART_NS16550_PORT_1_IRQ_PRI`	Port 1 Interrupt Priority
`CONFIG_UART_NS16550_PORT_1_BAUD_RATE`	Port 1 Baud Rate
`CONFIG_UART_NS16550_PORT_1_OPTIONS`	Port 1 Options
`CONFIG_UART_NS16550_PORT_1_DLF`	Port 1 DLF value
`CONFIG_UART_MCUX`	MCUX uart driver
`CONFIG_UART_MCUX_0`	UART 0
`CONFIG_UART_MCUX_0_NAME`	UART 0 driver name
`CONFIG_UART_MCUX_0_IRQ_PRI`	UART 0 interrupt priority
`CONFIG_UART_MCUX_0_BAUD_RATE`	UART 0 baud rate
`CONFIG_UART_MCUX_1`	UART 1
`CONFIG_UART_MCUX_1_NAME`	UART 1 driver name
`CONFIG_UART_MCUX_1_IRQ_PRI`	UART 1 interrupt priority
`CONFIG_UART_MCUX_1_BAUD_RATE`	UART 1 baud rate
`CONFIG_UART_MCUX_2`	UART 2
`CONFIG_UART_MCUX_2_NAME`	UART 2 driver name
`CONFIG_UART_MCUX_2_IRQ_PRI`	UART 2 interrupt priority
`CONFIG_UART_MCUX_2_BAUD_RATE`	UART 2 baud rate
`CONFIG_UART_MCUX_3`	UART 3
`CONFIG_UART_MCUX_3_NAME`	UART 3 driver name
`CONFIG_UART_MCUX_3_IRQ_PRI`	UART 3 interrupt priority
`CONFIG_UART_MCUX_3_BAUD_RATE`	UART 3 baud rate
`CONFIG_UART_MCUX_4`	UART 4
`CONFIG_UART_MCUX_4_NAME`	UART 4 driver name
`CONFIG_UART_MCUX_4_IRQ_PRI`	UART 4 interrupt priority
`CONFIG_UART_MCUX_4_BAUD_RATE`	UART 4 baud rate
`CONFIG_UART_MCUX_5`	UART 5
`CONFIG_UART_MCUX_5_NAME`	UART 5 driver name
`CONFIG_UART_MCUX_5_IRQ_PRI`	UART 5 interrupt priority
`CONFIG_UART_MCUX_5_BAUD_RATE`	UART 5 baud rate
`CONFIG_UART_MCUX_LPUART`	MCUX LPUART driver
`CONFIG_UART_MCUX_LPUART_0`	UART 0
`CONFIG_UART_MCUX_LPUART_0_NAME`	UART 0 driver name
`CONFIG_UART_MCUX_LPUART_0_IRQ_PRI`	UART 0 interrupt priority
`CONFIG_UART_MCUX_LPUART_0_BAUD_RATE`	UART 0 baud rate
`CONFIG_UART_STELLARIS`	Stellaris serial driver
`CONFIG_UART_STELLARIS_PORT_0`	Enable Stellaris UART Port 0
`CONFIG_UART_STELLARIS_PORT_0_NAME`	Port 0 Device Name
`CONFIG_UART_STELLARIS_PORT_0_IRQ_PRI`	Port 0 Interrupt Priority
`CONFIG_UART_STELLARIS_PORT_0_BAUD_RATE`	Port 0 Baud Rate
`CONFIG_UART_STELLARIS_PORT_1`	Enable Stellaris UART Port 1
`CONFIG_UART_STELLARIS_PORT_1_NAME`	Port 1 Device Name
`CONFIG_UART_STELLARIS_PORT_1_IRQ_PRI`	Port 1 Interrupt Priority
`CONFIG_UART_STELLARIS_PORT_1_BAUD_RATE`	Port 1 Baud Rate
`CONFIG_UART_STELLARIS_PORT_2`	Enable Stellaris UART Port 2
`CONFIG_UART_STELLARIS_PORT_2_NAME`	Port 2 Device Name
`CONFIG_UART_STELLARIS_PORT_2_IRQ_PRI`	Port 2 Interrupt Priority
`CONFIG_UART_STELLARIS_PORT_2_BAUD_RATE`	Port 2 Baud Rate
`CONFIG_UART_NSIM`	UART driver for MetaWare nSim
`CONFIG_UART_NSIM_PORT_0_NAME`	Port 0 Device Name
`CONFIG_UART_NSIM_PORT_0_BASE_ADDR`	Port 0 Register Address
`CONFIG_UART_ATMEL_SAM3`	Atmel SAM3 family processor UART driver
`CONFIG_UART_ATMEL_SAM3_NAME`	Device Name for Atmel SAM3 UART
`CONFIG_UART_ATMEL_SAM3_IRQ_PRI`	Atmel SAM3 UART Interrupt Priority
`CONFIG_UART_ATMEL_SAM3_BAUD_RATE`	Atmel SAM3 UART Baud Rate
`CONFIG_UART_ATMEL_SAM3_CLK_FREQ`	Atmel SAM3 UART Clock Frequency
`CONFIG_USART_SAM`	Atmel SAM MCU family USART driver
`CONFIG_USART_SAM_PORT_0`	Enable USART0
`CONFIG_USART_SAM_PORT_0_NAME`	USART0 Device Name
`CONFIG_USART_SAM_PORT_0_BAUD_RATE`	USART0 Baud Rate
`CONFIG_USART_SAM_PORT_1`	Enable USART1
`CONFIG_USART_SAM_PORT_1_NAME`	USART1 Device Name
`CONFIG_USART_SAM_PORT_1_BAUD_RATE`	USART1 Baud Rate
`CONFIG_USART_SAM_PORT_2`	Enable USART2
`CONFIG_USART_SAM_PORT_2_NAME`	USART2 Device Name
`CONFIG_USART_SAM_PORT_2_BAUD_RATE`	USART2 Baud Rate
`CONFIG_UART_QMSI`	QMSI UART driver
`CONFIG_UART_QMSI_0`	Enable UART 0 controller
`CONFIG_UART_QMSI_0_NAME`	UART_0 device name
`CONFIG_UART_QMSI_0_BAUDRATE`	UART_0 baud rate
`CONFIG_UART_QMSI_0_HW_FC`	HW flow control for UART_0 controller
`CONFIG_UART_QMSI_0_IRQ_PRI`	IRQ priority from UART_0 controller
`CONFIG_UART_QMSI_1`	Enable UART 1 controller
`CONFIG_UART_QMSI_1_NAME`	UART_1 device name
`CONFIG_UART_QMSI_1_BAUDRATE`	UART_1 baud rate
`CONFIG_UART_QMSI_1_HW_FC`	HW flow control for UART_1 controller
`CONFIG_UART_QMSI_1_IRQ_PRI`	IRQ priority from UART_1 controller
`CONFIG_UART_STM32`	STM32 MCU serial driver
`CONFIG_UART_STM32_PORT_1`	Enable STM32 USART1 Port
`CONFIG_UART_STM32_PORT_1_NAME`	Device Name for STM32 USART1 Port
`CONFIG_UART_STM32_PORT_1_BAUD_RATE`	STM32 USART1 Baud Rate
`CONFIG_UART_STM32_PORT_1_IRQ_PRI`	STM32 USART1 Interrupt Priority
`CONFIG_UART_STM32_PORT_2`	Enable STM32 USART2 Port
`CONFIG_UART_STM32_PORT_2_NAME`	Device Name for STM32 USART2 Port
`CONFIG_UART_STM32_PORT_2_BAUD_RATE`	STM32 USART2 Baud Rate
`CONFIG_UART_STM32_PORT_2_IRQ_PRI`	STM32 USART2 Interrupt Priority
`CONFIG_UART_STM32_PORT_3`	Enable STM32 USART3 Port
`CONFIG_UART_STM32_PORT_3_NAME`	Device Name for STM32 USART3 Port
`CONFIG_UART_STM32_PORT_3_BAUD_RATE`	STM32 USART3 Baud Rate
`CONFIG_UART_STM32_PORT_3_IRQ_PRI`	STM32 USART3 Interrupt Priority
`CONFIG_UART_NRF5`	Nordic Semiconductor NRF5 family processor UART driver
`CONFIG_UART_NRF5_NAME`	Device Name for Nordic Semiconductor nRF5 UART
`CONFIG_UART_NRF5_IRQ_PRI`	UART Interrupt Priority (Interrupt support)
`CONFIG_UART_NRF5_BAUD_RATE`	Baud Rate
`CONFIG_UART_NRF5_CLK_FREQ`
`CONFIG_UART_NRF5_FLOW_CONTROL`	Enable Flow Control
`CONFIG_UART_NRF5_GPIO_TX_PIN`	TX Pin Number
`CONFIG_UART_NRF5_GPIO_RX_PIN`	RX Pin Number
`CONFIG_UART_NRF5_GPIO_RTS_PIN`	RTS Pin Number
`CONFIG_UART_NRF5_GPIO_CTS_PIN`	CTS Pin Number
`CONFIG_UART_ALTERA_JTAG`	Nios II JTAG UART driver
`CONFIG_UART_CC32XX`	CC32XX UART driver
`CONFIG_UART_CC32XX_NAME`	Device Name for CC32XX UART
`CONFIG_UART_CC32XX_IRQ_PRI`	IRQ priority from UART controller
`CONFIG_UART_CC32XX_BAUDRATE`	UART_0 baud rate
`CONFIG_UART_CMSDK_APB`	ARM CMSDK APB UART driver
`CONFIG_UART_CMSDK_APB_PORT0`	Enable driver for UART 0
`CONFIG_UART_CMSDK_APB_PORT0_NAME`	Device Name for UART 0
`CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI`	UART Interrupt Priority (Interrupt support)
`CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE`	Baud Rate
`CONFIG_UART_CMSDK_APB_PORT1`	Enable driver for UART 1
`CONFIG_UART_CMSDK_APB_PORT1_NAME`	Device Name for UART 1
`CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI`	UART Interrupt Priority (Interrupt support)
`CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE`	Baud Rate
`CONFIG_UART_CMSDK_APB_PORT2`	Enable driver for UART 2
`CONFIG_UART_CMSDK_APB_PORT2_NAME`	Device Name for UART 2
`CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI`	UART Interrupt Priority (Interrupt support)
`CONFIG_UART_CMSDK_APB_PORT2_BAUD_RATE`	Baud Rate
`CONFIG_UART_CMSDK_APB_PORT3`	Enable driver for UART 3
`CONFIG_UART_CMSDK_APB_PORT3_NAME`	Device Name for UART 3
`CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI`	UART Interrupt Priority (Interrupt support)
`CONFIG_UART_CMSDK_APB_PORT3_BAUD_RATE`	Baud Rate
`CONFIG_UART_CMSDK_APB_PORT4`	Enable driver for UART 4
`CONFIG_UART_CMSDK_APB_PORT4_NAME`	Device Name for UART 4
`CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI`	UART Interrupt Priority (Interrupt support)
`CONFIG_UART_CMSDK_APB_PORT4_BAUD_RATE`	Baud Rate
`CONFIG_UART_RISCV_QEMU`	riscv-qemu UART driver
`CONFIG_LOAPIC`	LOAPIC
`CONFIG_LOAPIC_BASE_ADDRESS`	Local APIC Base Address
`CONFIG_LOAPIC_SPURIOUS_VECTOR`	Handle LOAPIC spurious interrupts
`CONFIG_LOAPIC_SPURIOUS_VECTOR_ID`	LOAPIC spurious vector ID
`CONFIG_IOAPIC`	IO-APIC
`CONFIG_IOAPIC_DEBUG`	IO-APIC Debugging
`CONFIG_IOAPIC_BASE_ADDRESS`	IO-APIC Base Address
`CONFIG_IOAPIC_NUM_RTES`	Number of Redirection Table Entries available
`CONFIG_IOAPIC_MASK_RTE`	Mask out RTE entries on boot
`CONFIG_MVIC`	Intel Quark D2000 Interrupt Controller (MVIC)
`CONFIG_MVIC_TIMER_IRQ`	IRQ line to use for timer interrupt
`CONFIG_ARCV2_INTERRUPT_UNIT`	ARCv2 Interrupt Unit
`CONFIG_EXTI_STM32`	External Interrupt/Event Controller (EXTI) Driver for STM32 family of MCUs
`CONFIG_EXTI_STM32_EXTI0_IRQ_PRI`	EXTI0 IRQ priority
`CONFIG_EXTI_STM32_EXTI1_IRQ_PRI`	EXTI1 IRQ priority
`CONFIG_EXTI_STM32_EXTI2_IRQ_PRI`	EXTI2 IRQ priority
`CONFIG_EXTI_STM32_EXTI3_IRQ_PRI`	EXTI3 IRQ priority
`CONFIG_EXTI_STM32_EXTI4_IRQ_PRI`	EXTI4 IRQ priority
`CONFIG_EXTI_STM32_EXTI9_5_IRQ_PRI`	EXTI9:5 IRQ priority
`CONFIG_EXTI_STM32_EXTI15_10_IRQ_PRI`	EXTI15:10 IRQ priority
`CONFIG_EXTI_STM32_EXTI16_IRQ_PRI`	EXTI16 IRQ priority
`CONFIG_EXTI_STM32_EXTI17_IRQ_PRI`	EXTI17 IRQ priority
`CONFIG_EXTI_STM32_EXTI18_IRQ_PRI`	EXTI18 IRQ priority
`CONFIG_EXTI_STM32_EXTI21_IRQ_PRI`	EXTI21 IRQ priority
`CONFIG_EXTI_STM32_EXTI22_IRQ_PRI`	EXTI22 IRQ priority
`CONFIG_HPET_TIMER`	HPET timer
`CONFIG_HPET_TIMER_LEGACY_EMULATION`	HPET timer legacy emulation mode
`CONFIG_HPET_TIMER_DEBUG`	Enable HPET debug output
`CONFIG_HPET_TIMER_BASE_ADDRESS`	HPET Base Address
`CONFIG_HPET_TIMER_IRQ`	HPET Timer IRQ
`CONFIG_HPET_TIMER_IRQ_PRIORITY`	HPET Timer IRQ Priority
`CONFIG_HPET_TIMER_FALLING_EDGE`	Falling Edge
`CONFIG_HPET_TIMER_RISING_EDGE`	Rising Edge
`CONFIG_HPET_TIMER_LEVEL_HIGH`	Level High
`CONFIG_HPET_TIMER_LEVEL_LOW`	Level Low
`CONFIG_LOAPIC_TIMER`	LOAPIC timer
`CONFIG_LOAPIC_TIMER_IRQ`	Local APIC Timer IRQ
`CONFIG_LOAPIC_TIMER_IRQ_PRIORITY`	Local APIC Timer IRQ Priority
`CONFIG_TSC_CYCLES_PER_SEC`	Frequency of x86 CPU timestamp counter
`CONFIG_ARCV2_TIMER`	ARC Timer
`CONFIG_ARCV2_TIMER_IRQ_PRIORITY`	ARC timer interrupt priority
`CONFIG_CORTEX_M_SYSTICK`	Cortex-M SYSTICK timer
`CONFIG_ALTERA_AVALON_TIMER`	Altera Avalon Interval Timer
`CONFIG_NRF_RTC_TIMER`	nRF Real Time Counter (NRF_RTC1) Timer
`CONFIG_PULPINO_TIMER`	pulpino Timer
`CONFIG_RISCV_MACHINE_TIMER`	RISCV Machine Timer
`CONFIG_XTENSA_TIMER`	Xtensa timer support
`CONFIG_XTENSA_INTERNAL_TIMER`	Xtensa internal timer
`CONFIG_XTENSA_TIMER_IRQ`	Xtensa external timer interrupt number
`CONFIG_XTENSA_TIMER_IRQ_PRIORITY`	Xtensa external timer interrupt priority
`CONFIG_SYSTEM_CLOCK_DISABLE`	API to disable system clock
`CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME`	Timer queries its hardware to find its frequency at runtime
`CONFIG_SYSTEM_CLOCK_INIT_PRIORITY`	System clock driver initialization priority
`CONFIG_RANDOM_GENERATOR`	Random Drivers
`CONFIG_RANDOM_MCUX`	MCUX Random driver
`CONFIG_RANDOM_HAS_DRIVER`
`CONFIG_RANDOM_NAME`	Random Device Name
`CONFIG_SYS_LOG_RANDOM_LEVEL`	Random Log level
`CONFIG_TEST_RANDOM_GENERATOR`	Non-random number generator
`CONFIG_X86_TSC_RANDOM_GENERATOR`	x86 timestamp counter based number generator
`CONFIG_TIMER_RANDOM_GENERATOR`	System timer clock based number generator
`CONFIG_GROVE`	Grove Device Drivers
`CONFIG_SYS_LOG_GROVE_LEVEL`	Grove Log level
`CONFIG_GROVE_LCD_RGB`	Enable the Seeed Grove LCD RGB Backlight
`CONFIG_GROVE_LCD_RGB_I2C_MASTER_DEV_NAME`	I2C Master where Grove LCD is connected
`CONFIG_GROVE_LIGHT_SENSOR`	Enable the Seeed Grove Light Sensor
`CONFIG_GROVE_LIGHT_SENSOR_NAME`	Driver name
`CONFIG_GROVE_LIGHT_SENSOR_ADC_DEV_NAME`	ADC where Grove Light Sensor is connected
`CONFIG_GROVE_LIGHT_SENSOR_ADC_CHANNEL`	ADC channel used by Grove Light Sensor
`CONFIG_GROVE_TEMPERATURE_SENSOR`	Enable the Seeed Grove Temperature Sensor
`CONFIG_GROVE_TEMPERATURE_SENSOR_NAME`	Driver name
`CONFIG_GROVE_TEMPERATURE_SENSOR_V1_0`	v1.0
`CONFIG_GROVE_TEMPERATURE_SENSOR_V1_X`	v1.1/v1.2
`CONFIG_GROVE_TEMPERATURE_SENSOR_ADC_DEV_NAME`	ADC where Grove Temperature Sensor is connected
`CONFIG_GROVE_TEMPERATURE_SENSOR_ADC_CHANNEL`	ADC channel used by Grove Temperature Sensor
`CONFIG_PCI`	PCI Settings
`CONFIG_PCI_ENUMERATION`	Enable PCI device enumeration
`CONFIG_PCI_LEGACY_BRIDGE`	PCI legacy bridge device support
`CONFIG_PCI_LEGACY_BRIDGE_BUS`	PCI Legacy Bridge Bus number
`CONFIG_PCI_LEGACY_BRIDGE_DEV`	PCI Legacy Bridge Device number
`CONFIG_PCI_LEGACY_BRIDGE_VENDOR_ID`	PCI Legacy Bridge Vendor ID
`CONFIG_PCI_LEGACY_BRIDGE_DEVICE_ID`	PCI Legacy Bridge Device ID
`CONFIG_PCI_DEBUG`	Enable PCI debugging
`CONFIG_GPIO`	GPIO Drivers
`CONFIG_SYS_LOG_GPIO_LEVEL`	GPIO drivers log level
`CONFIG_GPIO_DW`	Designware GPIO
`CONFIG_GPIO_DW_SHARED_IRQ`
`CONFIG_GPIO_DW_INIT_PRIORITY`	Init priority
`CONFIG_GPIO_DW_CLOCK_GATE`	Enable glock gating
`CONFIG_GPIO_DW_CLOCK_GATE_DRV_NAME`
`CONFIG_GPIO_DW_0`	Designware GPIO block 0
`CONFIG_GPIO_DW_0_NAME`	Driver name
`CONFIG_GPIO_DW_0_CLOCK_GATE_SUBSYS`	Clock controller’s subsystem
`CONFIG_GPIO_DW_0_IRQ_DIRECT`	Direct Hardware Interrupt
`CONFIG_GPIO_DW_0_IRQ_SHARED`	Shared IRQ
`CONFIG_GPIO_DW_0_IRQ_SHARED_NAME`	Device name for Shared IRQ
`CONFIG_GPIO_DW_0_IRQ_PRI`	Controller interrupt priority
`CONFIG_GPIO_DW_1`	Designware GPIO block 1
`CONFIG_GPIO_DW_1_NAME`	Driver name
`CONFIG_GPIO_DW_1_CLOCK_GATE_SUBSYS`	Clock controller’s subsystem
`CONFIG_GPIO_DW_1_IRQ_DIRECT`	Direct Hardware Interrupt
`CONFIG_GPIO_DW_1_IRQ_SHARED`	Shared IRQ
`CONFIG_GPIO_DW_1_IRQ_SHARED_NAME`	Device name for Shared IRQ
`CONFIG_GPIO_DW_1_IRQ_PRI`	Controller interrupt priority
`CONFIG_GPIO_DW_2`	Designware GPIO block 1
`CONFIG_GPIO_DW_2_NAME`	Driver name
`CONFIG_GPIO_DW_2_CLOCK_GATE_SUBSYS`	Clock controller’s subsystem
`CONFIG_GPIO_DW_2_IRQ_DIRECT`	Direct Hardware Interrupt
`CONFIG_GPIO_DW_2_IRQ_SHARED`	Shared IRQ
`CONFIG_GPIO_DW_2_IRQ_SHARED_NAME`	Device name for Shared IRQ
`CONFIG_GPIO_DW_2_IRQ_PRI`	Controller interrupt priority
`CONFIG_GPIO_DW_3`	Designware GPIO block 1
`CONFIG_GPIO_DW_3_NAME`	Driver name
`CONFIG_GPIO_DW_3_CLOCK_GATE_SUBSYS`	Clock controller’s subsystem
`CONFIG_GPIO_DW_3_IRQ_DIRECT`	Direct Hardware Interrupt
`CONFIG_GPIO_DW_3_IRQ_SHARED`	Shared IRQ
`CONFIG_GPIO_DW_3_IRQ_SHARED_NAME`	Device name for Shared IRQ
`CONFIG_GPIO_DW_3_IRQ_PRI`	Controller interrupt priority
`CONFIG_GPIO_PCAL9535A`	PCAL9535A I2C-based GPIO chip
`CONFIG_SYS_LOG_GPIO_PCAL9535A_LEVEL`	PCAL9535A driver log level
`CONFIG_GPIO_PCAL9535A_INIT_PRIORITY`	Init priority
`CONFIG_GPIO_PCAL9535A_0`	PCAL9535A GPIO chip #0
`CONFIG_GPIO_PCAL9535A_0_DEV_NAME`	PCAL9535A GPIO chip #0 Device Name
`CONFIG_GPIO_PCAL9535A_0_I2C_ADDR`	PCAL9535A GPIO chip #0 I2C slave address
`CONFIG_GPIO_PCAL9535A_0_I2C_MASTER_DEV_NAME`	I2C Master where PCAL9535A GPIO chip #0 is connected
`CONFIG_GPIO_PCAL9535A_1`	PCAL9535A GPIO chip #1
`CONFIG_GPIO_PCAL9535A_1_DEV_NAME`	PCAL9535A GPIO chip #1 Device Name
`CONFIG_GPIO_PCAL9535A_1_I2C_ADDR`	PCAL9535A GPIO chip #1 I2C slave address
`CONFIG_GPIO_PCAL9535A_1_I2C_MASTER_DEV_NAME`	I2C Master where PCAL9535A GPIO chip #1 is connected
`CONFIG_GPIO_PCAL9535A_2`	PCAL9535A GPIO chip #2
`CONFIG_GPIO_PCAL9535A_2_DEV_NAME`	PCAL9535A GPIO chip #2 Device Name
`CONFIG_GPIO_PCAL9535A_2_I2C_ADDR`	PCAL9535A GPIO chip #2 I2C slave address
`CONFIG_GPIO_PCAL9535A_2_I2C_MASTER_DEV_NAME`	I2C Master where PCAL9535A GPIO chip #2 is connected
`CONFIG_GPIO_PCAL9535A_3`	PCAL9535A GPIO chip #3
`CONFIG_GPIO_PCAL9535A_3_DEV_NAME`	PCAL9535A GPIO chip #3 Device Name
`CONFIG_GPIO_PCAL9535A_3_I2C_ADDR`	PCAL9535A GPIO chip #3 I2C slave address
`CONFIG_GPIO_PCAL9535A_3_I2C_MASTER_DEV_NAME`	I2C Master where PCAL9535A GPIO chip #3 is connected
`CONFIG_GPIO_QMSI`	QMSI GPIO driver
`CONFIG_GPIO_QMSI_SS`	QMSI GPIO SS driver
`CONFIG_GPIO_QMSI_INIT_PRIORITY`	Init priority
`CONFIG_GPIO_QMSI_API_REENTRANCY`	GPIO driver API reentrancy
`CONFIG_GPIO_QMSI_0`	QMSI GPIO block 0
`CONFIG_GPIO_QMSI_0_NAME`	Driver name
`CONFIG_GPIO_QMSI_0_IRQ_PRI`	Controller interrupt priority
`CONFIG_GPIO_QMSI_1`	QMSI GPIO block 1
`CONFIG_GPIO_QMSI_1_NAME`	Driver name
`CONFIG_GPIO_QMSI_1_IRQ_PRI`	Controller interrupt priority
`CONFIG_GPIO_QMSI_SS_0`	QMSI GPIO SS block 0
`CONFIG_GPIO_QMSI_SS_0_NAME`	Driver name
`CONFIG_GPIO_QMSI_SS_0_IRQ_PRI`	Controller interrupt priority
`CONFIG_GPIO_QMSI_SS_1`	QMSI GPIO SS block 1
`CONFIG_GPIO_QMSI_SS_1_NAME`	Driver name
`CONFIG_GPIO_QMSI_SS_1_IRQ_PRI`	Controller interrupt priority
`CONFIG_GPIO_SCH`	Intel SCH GPIO controller
`CONFIG_GPIO_SCH_INIT_PRIORITY`	Init priority
`CONFIG_GPIO_SCH_0`	Enable SCH GPIO port 0
`CONFIG_GPIO_SCH_0_DEV_NAME`	Name of the device
`CONFIG_GPIO_SCH_1`	Enable SCH GPIO port 1
`CONFIG_GPIO_SCH_1_DEV_NAME`	Name of the device
`CONFIG_GPIO_MCUX`	MCUX GPIO driver
`CONFIG_GPIO_MCUX_PORTA`	Port A
`CONFIG_GPIO_MCUX_PORTA_NAME`	Port A driver name
`CONFIG_GPIO_MCUX_PORTA_PRI`	Port A interrupt priority
`CONFIG_GPIO_MCUX_PORTB`	Port B
`CONFIG_GPIO_MCUX_PORTB_NAME`	Port B driver name
`CONFIG_GPIO_MCUX_PORTB_PRI`	Port B interrupt priority
`CONFIG_GPIO_MCUX_PORTC`	Port C
`CONFIG_GPIO_MCUX_PORTC_NAME`	Port C driver name
`CONFIG_GPIO_MCUX_PORTC_PRI`	Port C interrupt priority
`CONFIG_GPIO_MCUX_PORTD`	Port D
`CONFIG_GPIO_MCUX_PORTD_NAME`	Port D driver name
`CONFIG_GPIO_MCUX_PORTD_PRI`	Port D interrupt priority
`CONFIG_GPIO_MCUX_PORTE`	Port E
`CONFIG_GPIO_MCUX_PORTE_NAME`	Port E driver name
`CONFIG_GPIO_MCUX_PORTE_PRI`	Port E interrupt priority
`CONFIG_GPIO_ATMEL_SAM3`	Atmel SAM3 PIO Controllers
`CONFIG_GPIO_ATMEL_SAM3_PORTA`	Enable driver for Atmel SAM3 PIO Port A
`CONFIG_GPIO_ATMEL_SAM3_PORTA_DEV_NAME`	Device name for Port A
`CONFIG_GPIO_ATMEL_SAM3_PORTA_IRQ_PRI`	Interrupt Priority for Port A
`CONFIG_GPIO_ATMEL_SAM3_PORTB`	Enable driver for Atmel SAM3 PIO Port B
`CONFIG_GPIO_ATMEL_SAM3_PORTB_DEV_NAME`	Device name for Port B
`CONFIG_GPIO_ATMEL_SAM3_PORTB_IRQ_PRI`	Interrupt Priority for Port B
`CONFIG_GPIO_ATMEL_SAM3_PORTC`	Enable driver for Atmel SAM3 PIO Port C
`CONFIG_GPIO_ATMEL_SAM3_PORTC_DEV_NAME`	Device name for Port C
`CONFIG_GPIO_ATMEL_SAM3_PORTC_IRQ_PRI`	Interrupt Priority for Port C
`CONFIG_GPIO_ATMEL_SAM3_PORTD`	Enable driver for Atmel SAM3 PIO Port D
`CONFIG_GPIO_ATMEL_SAM3_PORTD_DEV_NAME`	Device name for Port D
`CONFIG_GPIO_ATMEL_SAM3_PORTD_IRQ_PRI`	Interrupt Priority for Port D
`CONFIG_GPIO_STM32`	GPIO Driver for STM32 family of MCUs
`CONFIG_GPIO_STM32_PORTA`	Enable GPIO port A support
`CONFIG_GPIO_STM32_PORTB`	Enable GPIO port B support
`CONFIG_GPIO_STM32_PORTC`	Enable GPIO port C support
`CONFIG_GPIO_STM32_PORTD`	Enable GPIO port D support
`CONFIG_GPIO_STM32_PORTE`	Enable GPIO port E support
`CONFIG_GPIO_STM32_PORTF`	Enable GPIO port F support
`CONFIG_GPIO_STM32_PORTG`	Enable GPIO port G support
`CONFIG_GPIO_STM32_PORTH`	Enable GPIO port H support
`CONFIG_GPIO_NRF5`	Nordic Semiconductor nRF5X-based GPIO driver
`CONFIG_GPIO_NRF5_P0`	nRF5x GPIO Port P0 options
`CONFIG_GPIO_NRF5_P0_DEV_NAME`	GPIO Port P0 Device Name
`CONFIG_GPIO_NRF5_PORT_P0_PRI`	GPIOTE P0 interrupt priority
`CONFIG_GPIO_CMSDK_AHB`	ARM CMSDK (Cortex-M System Design Kit) AHB GPIO Controllers
`CONFIG_GPIO_CMSDK_AHB_PORT0`	Enable driver for GPIO Port 0
`CONFIG_GPIO_CMSDK_AHB_PORT0_DEV_NAME`	Device name for Port 0
`CONFIG_GPIO_CMSDK_AHB_PORT0_IRQ_PRI`	Interrupt Priority for Port 0
`CONFIG_GPIO_CMSDK_AHB_PORT1`	Enable driver for GPIO Port 1
`CONFIG_GPIO_CMSDK_AHB_PORT1_DEV_NAME`	Device name for Port 1
`CONFIG_GPIO_CMSDK_AHB_PORT1_IRQ_PRI`	Interrupt Priority for Port 1
`CONFIG_GPIO_CMSDK_AHB_PORT2`	Enable driver for GPIO Port 2
`CONFIG_GPIO_CMSDK_AHB_PORT2_DEV_NAME`	Device name for Port 2
`CONFIG_GPIO_CMSDK_AHB_PORT2_IRQ_PRI`	Interrupt Priority for Port 2
`CONFIG_GPIO_CMSDK_AHB_PORT3`	Enable driver for GPIO Port 3
`CONFIG_GPIO_CMSDK_AHB_PORT3_DEV_NAME`	Device name for Port 3
`CONFIG_GPIO_CMSDK_AHB_PORT3_IRQ_PRI`	Interrupt Priority for Port 3
`CONFIG_GPIO_CC32XX`	TI CC32XX GPIO driver
`CONFIG_GPIO_CC32XX_A0`	GPIO block A0
`CONFIG_GPIO_CC32XX_A0_NAME`	Driver name
`CONFIG_GPIO_CC32XX_A0_IRQ_PRI`	GPIO A0 interrupt priority
`CONFIG_GPIO_CC32XX_A1`	GPIO block A1
`CONFIG_GPIO_CC32XX_A1_NAME`	Driver name
`CONFIG_GPIO_CC32XX_A1_IRQ_PRI`	GPIO A1 interrupt priority
`CONFIG_GPIO_CC32XX_A2`	GPIO block A2
`CONFIG_GPIO_CC32XX_A2_NAME`	Driver name
`CONFIG_GPIO_CC32XX_A2_IRQ_PRI`	GPIO A2 interrupt priority
`CONFIG_GPIO_CC32XX_A3`	GPIO block A3
`CONFIG_GPIO_CC32XX_A3_NAME`	Driver name
`CONFIG_GPIO_CC32XX_A3_IRQ_PRI`	GPIO A3 interrupt priority
`CONFIG_GPIO_PULPINO`	Pulpino GPIO controller driver
`CONFIG_SHARED_IRQ`	Shared interrupt driver
`CONFIG_SHARED_IRQ_NUM_CLIENTS`	The number of clients per instance
`CONFIG_SHARED_IRQ_INIT_PRIORITY`	Shared IRQ init priority
`CONFIG_SHARED_IRQ_0`	Shared interrupt instance 0
`CONFIG_SHARED_IRQ_0_NAME`	Select a name for the device
`CONFIG_SHARED_IRQ_0_IRQ`	instance 0 interrupt
`CONFIG_SHARED_IRQ_0_PRI`	instance 0 interrupt priority
`CONFIG_SHARED_IRQ_0_FALLING_EDGE`	Falling Edge
`CONFIG_SHARED_IRQ_0_RISING_EDGE`	Rising Edge
`CONFIG_SHARED_IRQ_0_LEVEL_HIGH`	Level High
`CONFIG_SHARED_IRQ_0_LEVEL_LOW`	Level Low
`CONFIG_SHARED_IRQ_1`	Shared interrupt instance 1
`CONFIG_SHARED_IRQ_1_NAME`	Select a name for the device
`CONFIG_SHARED_IRQ_1_IRQ`	instance 1 interrupt
`CONFIG_SHARED_IRQ_1_PRI`	instance 1 interrupt priority
`CONFIG_SHARED_IRQ_1_FALLING_EDGE`	Falling Edge
`CONFIG_SHARED_IRQ_1_RISING_EDGE`	Rising Edge
`CONFIG_SHARED_IRQ_1_LEVEL_HIGH`	Level High
`CONFIG_SHARED_IRQ_1_LEVEL_LOW`	Level Low
`CONFIG_SPI`	SPI hardware bus support
`CONFIG_SPI_QMSI`	QMSI driver for SPI controller
`CONFIG_SPI_QMSI_SS`	QMSI driver for SPI controller on Sensor Subsystem
`CONFIG_SPI_INTEL`	Intel SPI controller driver
`CONFIG_SPI_INIT_PRIORITY`	Init priority
`CONFIG_SYS_LOG_SPI_LEVEL`	SPI Driver Log level
`CONFIG_SPI_CS_GPIO`	SPI port CS pin is controlled via a GPIO port
`CONFIG_SPI_0`	SPI port 0
`CONFIG_SPI_0_NAME`	SPI port 0 device name
`CONFIG_SPI_0_IRQ_PRI`	Port 0 interrupt priority
`CONFIG_SPI_0_DEFAULT_CFG`	Port 0 default configuration
`CONFIG_SPI_0_DEFAULT_BAUD_RATE`	Port 0 default baud rate
`CONFIG_SPI_0_CS_GPIO_PORT`	The GPIO port which is used to control CS
`CONFIG_SPI_0_CS_GPIO_PIN`	The GPIO PIN which is used to act as a CS pin
`CONFIG_SPI_1`	SPI port 1
`CONFIG_SPI_1_NAME`	SPI port 1 device name
`CONFIG_SPI_1_IRQ_PRI`	Port 0 interrupt priority
`CONFIG_SPI_1_DEFAULT_CFG`	Port 1 default configuration
`CONFIG_SPI_1_DEFAULT_BAUD_RATE`	Port 1 default baud rate
`CONFIG_SPI_1_CS_GPIO_PORT`	The GPIO port which is used to control CS
`CONFIG_SPI_1_CS_GPIO_PIN`	The GPIO PIN which is used to act as a CS pin
`CONFIG_SPI_2`	SPI port 2
`CONFIG_SPI_2_NAME`	SPI port 2 device name
`CONFIG_SPI_2_IRQ_PRI`	Port 2 interrupt priority
`CONFIG_SPI_2_DEFAULT_CFG`	Port 2 default configuration
`CONFIG_SPI_2_DEFAULT_BAUD_RATE`	Port 2 default baud rate
`CONFIG_SPI_2_CS_GPIO_PORT`	The GPIO port which is used to control CS
`CONFIG_SPI_2_CS_GPIO_PIN`	The GPIO PIN which is used to act as a CS pin
`CONFIG_SPI_SS_INIT_PRIORITY`	Init priority
`CONFIG_SPI_SS_CS_GPIO`	SPI port CS pin is controlled via a GPIO port
`CONFIG_SPI_SS_0`	SPI SS port 0
`CONFIG_SPI_SS_0_NAME`	SPI SS port 0 device name
`CONFIG_SPI_SS_0_IRQ_PRI`	Port 0 interrupt priority
`CONFIG_SPI_SS_0_CS_GPIO_PORT`	The GPIO port which is used to control CS
`CONFIG_SPI_SS_0_CS_GPIO_PIN`	The GPIO PIN which is used to act as a CS pin
`CONFIG_SPI_SS_1`	SPI SS port 1
`CONFIG_SPI_SS_1_NAME`	SPI port 1 device name
`CONFIG_SPI_SS_1_IRQ_PRI`	Port 0 interrupt priority
`CONFIG_SPI_SS_1_CS_GPIO_PORT`	The GPIO port which is used to control CS
`CONFIG_SPI_SS_1_CS_GPIO_PIN`	The GPIO PIN which is used to act as a CS pin
`CONFIG_SPI_DW`	Designware SPI controller driver
`CONFIG_SPI_DW_ARC_AUX_REGS`	Registers are part of ARC auxiliary registers
`CONFIG_SPI_DW_INTERRUPT_SINGLE_LINE`	Single interrupt line for all interrupts
`CONFIG_SPI_DW_INTERRUPT_SEPARATED_LINES`	One line per-interrupt type (RX, TX and ERROR)
`CONFIG_SPI_DW_CLOCK_GATE`	Enable glock gating
`CONFIG_SPI_DW_CLOCK_GATE_DRV_NAME`
`CONFIG_SPI_DW_FIFO_DEPTH`	Rx and Tx FIFO Depth
`CONFIG_SPI_DW_PORT_0_CLOCK_GATE_SUBSYS`	Clock controller’s subsystem
`CONFIG_SPI_DW_PORT_1_CLOCK_GATE_SUBSYS`	Clock controller’s subsystem
`CONFIG_SPI_MCUX`	MCUX SPI driver
`CONFIG_SPI_MCUX_BUF_SIZE`	Number of bytes in the local buffer
`CONFIG_SPI_MCUX_DUMMY_CHAR`	Dummy character
`CONFIG_I2C`	I2C Drivers
`CONFIG_I2C_DW`	Design Ware I2C support
`CONFIG_I2C_QMSI_SS`	QMSI I2C driver for the Sensor Subsystem
`CONFIG_I2C_QMSI`	QMSI I2C driver
`CONFIG_I2C_ATMEL_SAM3`	Atmel SAM3 I2C Driver
`CONFIG_I2C_MCUX`	MCUX I2C driver
`CONFIG_I2C_NRF5`	NRF5 I2C driver
`CONFIG_I2C_NRF5_GPIO_SCA_PIN`	SCA Pin Number
`CONFIG_I2C_NRF5_GPIO_SCL_PIN`	SCL Pin Number
`CONFIG_I2C_STM32LX`	STM32Lx MCU I2C Driver
`CONFIG_I2C_STM32LX_INTERRUPT`	STM32Lx MCU I2C Interrupt Support
`CONFIG_I2C_INIT_PRIORITY`	Init priority
`CONFIG_I2C_CLOCK_SPEED`	Set the clock speed for I2C
`CONFIG_SYS_LOG_I2C_LEVEL`	I2C log level
`CONFIG_I2C_SHARED_IRQ`
`CONFIG_I2C_0_IRQ_DIRECT`	Direct Hardware Interrupt
`CONFIG_I2C_0_IRQ_SHARED`	Shared IRQ
`CONFIG_I2C_0_IRQ_SHARED_NAME`	Device name for Shared IRQ
`CONFIG_I2C_0`	Enable I2C_0
`CONFIG_I2C_0_NAME`	Select a name for finding the device
`CONFIG_I2C_0_DEFAULT_CFG`	I2C default configuration
`CONFIG_I2C_0_IRQ_PRI`	Controller interrupt priority
`CONFIG_I2C_1`	Enable I2C Port 1
`CONFIG_I2C_1_NAME`	Select a name for finding the device
`CONFIG_I2C_1_DEFAULT_CFG`	I2C default configuration
`CONFIG_I2C_1_IRQ_PRI`	Controller interrupt priority
`CONFIG_I2C_SS_0`	Enable I2C_SS_0
`CONFIG_I2C_SS_0_NAME`	Select a name for finding the device
`CONFIG_I2C_SS_0_DEFAULT_CFG`	I2C default configuration
`CONFIG_I2C_SS_1`	Enable I2C SS Port 1
`CONFIG_I2C_SS_1_NAME`	Select a name for finding the device
`CONFIG_I2C_SS_1_DEFAULT_CFG`	I2C SS default configuration
`CONFIG_I2C_SS_SDA_HOLD`
`CONFIG_I2C_SS_SDA_SETUP`
`CONFIG_I2C_SDA_SETUP`
`CONFIG_I2C_SDA_TX_HOLD`
`CONFIG_I2C_SDA_RX_HOLD`
`CONFIG_PWM`	PWM (Pulse Width Modulation) Drivers
`CONFIG_PWM_PCA9685`	PCA9685 I2C-based PWM chip
`CONFIG_PWM_PCA9685_INIT_PRIORITY`	Init priority
`CONFIG_PWM_PCA9685_0`	PCA9685 PWM chip #0
`CONFIG_PWM_PCA9685_0_DEV_NAME`	PCA9685 PWM chip #0 Device Name
`CONFIG_PWM_PCA9685_0_I2C_ADDR`	PCA9685 PWM chip #0 I2C slave address
`CONFIG_PWM_PCA9685_0_I2C_MASTER_DEV_NAME`	I2C Master where PCA9685 PWM chip #0 is connected
`CONFIG_PWM_QMSI`	QMSI PWM Driver
`CONFIG_PWM_QMSI_DEV_NAME`	QMSI PWM Device Name
`CONFIG_PWM_QMSI_NUM_PORTS`	Number of PWM ports for PWM
`CONFIG_PWM_QMSI_API_REENTRANCY`	PWM shim driver API reentrancy
`CONFIG_PWM_DW`	DesignWare PWM
`CONFIG_PWM_DW_0_DRV_NAME`	DesignWare PWM Device Name
`CONFIG_PWM_K64_FTM`	PWM with Freescale K64 Flex Timer Module (FTM)
`CONFIG_SYS_LOG_PWM_K64_FTM_LEVEL`	Sets log level for pwm_ftm driver
`CONFIG_PWM_K64_FTM_0`	K64 FTM PWM Module 0
`CONFIG_PWM_K64_FTM_0_DEV_NAME`	K64 FTM PWM Module 0 Device Name
`CONFIG_PWM_K64_FTM_0_PRESCALE`	K64 FTM0 prescale value
`CONFIG_PWM_K64_FTM_0_PERIOD`	K64 FTM0 period value
`CONFIG_PWM_K64_FTM_0_CLOCK_SOURCE_NONE`	No clock selected (FTM counter disable)
`CONFIG_PWM_K64_FTM_0_CLOCK_SOURCE_SYSTEM`	System clock
`CONFIG_PWM_K64_FTM_0_CLOCK_SOURCE_FIXED`	Fixed Frequency Clock
`CONFIG_PWM_K64_FTM_0_CLOCK_SOURCE_EXTERNAL`	External Clock
`CONFIG_PWM_K64_FTM_0_CLOCK_SOURCE_QUAD`	Quadrature Decoder
`CONFIG_PWM_K64_FTM_0_CLOCK_SOURCE`
`CONFIG_PWM_K64_FTM_0_PHASE_ENABLE_0`	FTM0 Enable Phase for channel 0
`CONFIG_PWM_K64_FTM_0_PHASE_ENABLE_2`	FTM0 Enable Phase for channel 2
`CONFIG_PWM_K64_FTM_0_PHASE_ENABLE_4`	FTM0 Enable Phase for channel 4
`CONFIG_PWM_K64_FTM_0_PHASE_ENABLE_6`	FTM0 Enable Phase for channel 6
`CONFIG_PWM_K64_FTM_1`	K64 FTM PWM Module 1
`CONFIG_PWM_K64_FTM_1_DEV_NAME`	K64 FTM PWM Module 1 Device Name
`CONFIG_PWM_K64_FTM_1_PRESCALE`	FTM1 prescale value
`CONFIG_PWM_K64_FTM_1_PERIOD`	FTM1 period value
`CONFIG_PWM_K64_FTM_1_CLOCK_SOURCE_NONE`	No clock selected (FTM counter disable)
`CONFIG_PWM_K64_FTM_1_CLOCK_SOURCE_SYSTEM`	System clock
`CONFIG_PWM_K64_FTM_1_CLOCK_SOURCE_FIXED`	Fixed Frequency Clock
`CONFIG_PWM_K64_FTM_1_CLOCK_SOURCE_EXTERNAL`	External Clock
`CONFIG_PWM_K64_FTM_1_CLOCK_SOURCE_QUAD`	Quadrature Decoder
`CONFIG_PWM_K64_FTM_1_CLOCK_SOURCE`
`CONFIG_PWM_K64_FTM_1_PHASE_ENABLE_0`	FTM1 Enable Phase for channel 0
`CONFIG_PWM_FTM_1_PHASE_ENABLE_2`	FTM1 Enable Phase for channel 2
`CONFIG_PWM_FTM_1_PHASE_ENABLE_4`	FTM1 Enable Phase for channel 4
`CONFIG_PWM_FTM_1_PHASE_ENABLE_6`	FTM1 Enable Phase for channel 6
`CONFIG_PWM_K64_FTM_2`	K64 FTM PWM Module 2
`CONFIG_PWM_K64_FTM_2_DEV_NAME`	K64 FTM PWM Module 2 Device Name
`CONFIG_PWM_K64_FTM_2_PRESCALE`	FTM2 prescale value
`CONFIG_PWM_K64_FTM_2_PERIOD`	FTM2 period value
`CONFIG_PWM_K64_FTM_2_CLOCK_SOURCE_NONE`	No clock selected (FTM counter disable)
`CONFIG_PWM_K64_FTM_2_CLOCK_SOURCE_SYSTEM`	System clock
`CONFIG_PWM_K64_FTM_2_CLOCK_SOURCE_FIXED`	Fixed Frequency Clock
`CONFIG_PWM_K64_FTM_2_CLOCK_SOURCE_EXTERNAL`	External Clock
`CONFIG_PWM_K64_FTM_2_CLOCK_SOURCE_QUAD`	Quadrature Decoder
`CONFIG_PWM_K64_FTM_2_CLOCK_SOURCE`
`CONFIG_PWM_K64_FTM_2_PHASE_ENABLE_0`	FTM2 Enable Phase for channel 0
`CONFIG_PWM_K64_FTM_2_PHASE_ENABLE_2`	FTM2 Enable Phase for channel 2
`CONFIG_PWM_K64_FTM_2_PHASE_ENABLE_4`	FTM2 Enable Phase for channel 4
`CONFIG_PWM_K64_FTM_2_PHASE_ENABLE_6`	FTM2 Enable Phase for channel 6
`CONFIG_PWM_K64_FTM_3`	K64 FTM PWM Module 3
`CONFIG_PWM_K64_FTM_3_DEV_NAME`	K64 FTM PWM Module 3 Device Name
`CONFIG_PWM_K64_FTM_3_PRESCALE`	FTM3 prescale value
`CONFIG_PWM_K64_FTM_3_PERIOD`	FTM3 period value
`CONFIG_PWM_K64_FTM_3_CLOCK_SOURCE_NONE`	No clock selected (FTM counter disable)
`CONFIG_PWM_K64_FTM_3_CLOCK_SOURCE_SYSTEM`	System clock
`CONFIG_PWM_K64_FTM_3_CLOCK_SOURCE_FIXED`	Fixed Frequency Clock
`CONFIG_PWM_K64_FTM_3_CLOCK_SOURCE_EXTERNAL`	External Clock
`CONFIG_PWM_K64_FTM_3_CLOCK_SOURCE_QUAD`	Quadrature Decoder
`CONFIG_PWM_K64_FTM_3_CLOCK_SOURCE`
`CONFIG_PWM_K64_FTM_3_PHASE_ENABLE_0`	FTM3 Enable Phase for channel 0
`CONFIG_PWM_K64_FTM_3_PHASE_ENABLE_2`	FTM3 Enable Phase for channel 2
`CONFIG_PWM_K64_FTM_3_PHASE_ENABLE_4`	FTM3 Enable Phase for channel 4
`CONFIG_PWM_K64_FTM_3_PHASE_ENABLE_6`	FTM3 Enable Phase for channel 6
`CONFIG_PWM_STM32`	STM32 MCU PWM driver
`CONFIG_PWM_STM32_1`	STM32 PWM 1 Output
`CONFIG_PWM_STM32_1_DEV_NAME`	STM32 PWM Device Name
`CONFIG_PWM_STM32_2`	STM32 PWM 2 Output
`CONFIG_PWM_STM32_2_DEV_NAME`	STM32 PWM Device Name
`CONFIG_PINMUX`	Enable board pinmux driver
`CONFIG_PINMUX_DEV`	Configure pinmux for early board testing
`CONFIG_PINMUX_DEV_NAME`	Configure pinmux for early board testing
`CONFIG_PINMUX_DEV_ATMEL_SAM3X`	Enable pinmux dev driver for Atmel SAM3X boards
`CONFIG_PINMUX_DEV_K64`	Enable the pinmux dev driver for Freescale K64
`CONFIG_PINMUX_DEV_STM32`	Enable pinmux dev driver for the ST STM32 family.
`CONFIG_PINMUX_DEV_ARM_V2M_BEETLE`	Enable pinmux dev driver for ARM V2M Beetle boards
`CONFIG_PINMUX_NAME`	Pinmux driver name
`CONFIG_PINMUX_INIT_PRIORITY`	Init priority
`CONFIG_PINMUX_QMSI`	Enable QMSI pinmux dev driver
`CONFIG_PINMUX_MCUX`	MCUX pinmux driver
`CONFIG_PINMUX_MCUX_PORTA`	Port A
`CONFIG_PINMUX_MCUX_PORTA_NAME`	Pinmux Port A driver name
`CONFIG_PINMUX_MCUX_PORTB`	Port B
`CONFIG_PINMUX_MCUX_PORTB_NAME`	Pinmux Port B driver name
`CONFIG_PINMUX_MCUX_PORTC`	Port C
`CONFIG_PINMUX_MCUX_PORTC_NAME`	Pinmux Port C driver name
`CONFIG_PINMUX_MCUX_PORTD`	Port D
`CONFIG_PINMUX_MCUX_PORTD_NAME`	Pinmux Port D driver name
`CONFIG_PINMUX_MCUX_PORTE`	Port E
`CONFIG_PINMUX_MCUX_PORTE_NAME`	Pinmux Port E driver name
`CONFIG_PINMUX_STM32`	Pinmux driver for STM32 MCUs
`CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY`	Device initialization priority STM32 pinmux
`CONFIG_PINMUX_BEETLE`	ARM V2M Beetle Pin multiplexer driver
`CONFIG_ADC`	ADC drivers
`CONFIG_SYS_LOG_ADC_LEVEL`	ADC drivers log level
`CONFIG_ADC_INIT_PRIORITY`	Init priority
`CONFIG_ADC_0_NAME`	ADC Driver’s name
`CONFIG_ADC_0_IRQ_PRI`	ADC interrupt priority
`CONFIG_ADC_TI_ADC108S102`	TI adc108s102 chip driver
`CONFIG_ADC_TI_ADC108S102_SPI_PORT_NAME`	Master SPI port name
`CONFIG_ADC_TI_ADC108S102_SPI_CONFIGURATION`	Master SPI port configuration
`CONFIG_ADC_TI_ADC108S102_SPI_MAX_FREQ`	Master SPI port max frequency
`CONFIG_ADC_TI_ADC108S102_SPI_SLAVE`	SPI slave slot
`CONFIG_ADC_DW`	ARC Designware Driver
`CONFIG_ADC_DW_CALIBRATION`	Enable Calibration
`CONFIG_ADC_DW_DUMMY_CONVERSION`	Enable dummy conversion
`CONFIG_ADC_DW_SERIAL`	Serial
`CONFIG_ADC_DW_PARALLEL`	Parallel
`CONFIG_ADC_DW_SINGLESHOT`	Single Ended
`CONFIG_ADC_DW_REPETITIVE`	Differential
`CONFIG_ADC_DW_RISING_EDGE`	Rising Edge
`CONFIG_ADC_DW_FALLING_EDGE`	Falling Edge
`CONFIG_ADC_DW_SAMPLE_WIDTH`	Sample Width
`CONFIG_ADC_DW_SERIAL_DELAY`	Serial Delay
`CONFIG_ADC_DW_CLOCK_RATIO`	Clock Ratio
`CONFIG_ADC_QMSI`	QMSI ADC Driver
`CONFIG_ADC_QMSI_SS`	QMSI ADC Driver for the Sensor Subsystem
`CONFIG_ADC_QMSI_POLL`	Polling samples
`CONFIG_ADC_QMSI_INTERRUPT`	Interrupt notification
`CONFIG_ADC_QMSI_CALIBRATION`	Enable Calibration
`CONFIG_ADC_QMSI_CLOCK_RATIO`	Clock Ratio
`CONFIG_ADC_QMSI_SERIAL_DELAY`	Serial Delay
`CONFIG_ADC_QMSI_SAMPLE_WIDTH`	Sample Width
`CONFIG_RTC`	Real-Time Clock
`CONFIG_RTC_QMSI`	QMSI RTC Driver
`CONFIG_RTC_0_NAME`	Driver instance name
`CONFIG_RTC_0_IRQ_PRI`	RTC Driver Interrupt priority
`CONFIG_RTC_QMSI_API_REENTRANCY`	RTC shim driver API reentrancy
`CONFIG_WATCHDOG`	Watchdog Support
`CONFIG_WDT_QMSI`	QMSI Watchdog driver
`CONFIG_WDT_0_NAME`	Watchdog driver instance name
`CONFIG_WDT_0_IRQ_PRI`	Interrupt priority
`CONFIG_WDT_QMSI_API_REENTRANCY`	WDT shim driver API reentrancy
`CONFIG_IWDG_STM32`	Independent Watchdog (IWDG) Driver for STM32 family of MCUs
`CONFIG_IWDG_STM32_PRESCALER`	Prescaler divider for clock feeding the IWDG
`CONFIG_IWDG_STM32_RELOAD_COUNTER`	Value for IWDG counter
`CONFIG_IWDG_STM32_START_AT_BOOT`	Start IWDG during boot
`CONFIG_IWDG_STM32_DEVICE_NAME`	Device name for Independent Watchdog (IWDG)
`CONFIG_WDOG_CMSDK_APB`	CMSDK APB Watchdog Driver for ARM family of MCUs
`CONFIG_WDOG_CMSDK_APB_START_AT_BOOT`	Start Watchdog during boot
`CONFIG_WDOG_CMSDK_APB_DEVICE_NAME`	Device name for CMSDK APB Watchdog
`CONFIG_CLOCK_CONTROL`	Hardware clock controller support
`CONFIG_SYS_LOG_CLOCK_CONTROL_LEVEL`	Hardware clock controller drivers log level
`CONFIG_CLOCK_CONTROL_NRF5`	NRF5 Clock controller support
`CONFIG_CLOCK_CONTROL_NRF5_IRQ_PRIORITY`	Power Clock Interrupt Priority
`CONFIG_CLOCK_CONTROL_NRF5_M16SRC_DRV_NAME`	NRF5 16MHz clock device name
`CONFIG_CLOCK_CONTROL_NRF5_K32SRC_DRV_NAME`	NRF5 32KHz clock device name
`CONFIG_CLOCK_CONTROL_NRF5_K32SRC_RC`	RC Oscillator
`CONFIG_CLOCK_CONTROL_NRF5_K32SRC_XTAL`	Crystal Oscillator
`CONFIG_CLOCK_CONTROL_NRF5_K32SRC_500PPM`	251 ppm to 500 ppm
`CONFIG_CLOCK_CONTROL_NRF5_K32SRC_250PPM`	151 ppm to 250 ppm
`CONFIG_CLOCK_CONTROL_NRF5_K32SRC_150PPM`	101 ppm to 150 ppm
`CONFIG_CLOCK_CONTROL_NRF5_K32SRC_100PPM`	76 ppm to 100 ppm
`CONFIG_CLOCK_CONTROL_NRF5_K32SRC_75PPM`	51 ppm to 75 ppm
`CONFIG_CLOCK_CONTROL_NRF5_K32SRC_50PPM`	31 ppm to 50 ppm
`CONFIG_CLOCK_CONTROL_NRF5_K32SRC_30PPM`	21 ppm to 30 ppm
`CONFIG_CLOCK_CONTROL_NRF5_K32SRC_20PPM`	0 ppm to 20 ppm
`CONFIG_CLOCK_CONTROL_QUARK_SE`	Quark SE Clock controller support
`CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL`	Quark SE peripheral clock support
`CONFIG_CLOCK_CONTROL_QUARK_SE_PERIPHERAL_DRV_NAME`	Quark SE peripheral clock device name
`CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL`	Quark SE external clock support
`CONFIG_CLOCK_CONTROL_QUARK_SE_EXTERNAL_DRV_NAME`	Quark SE external clock device name
`CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR`	Quark SE sensor clock support
`CONFIG_CLOCK_CONTROL_QUARK_SE_SENSOR_DRV_NAME`	Quark SE sensor clock device name
`CONFIG_CLOCK_CONTROL_STM32_CUBE`	STM32 Reset & Clock Control
`CONFIG_CLOCK_CONTROL_STM32_DEVICE_INIT_PRIORITY`	Clock Control Device Priority
`CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE`	HSE
`CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI`	HSI
`CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL`	PLL
`CONFIG_CLOCK_STM32_HSE_BYPASS`	HSE bypass
`CONFIG_CLOCK_STM32_HSE_CLOCK`	HSE clock value
`CONFIG_CLOCK_STM32_PLL_SRC_MSI`	MSI
`CONFIG_CLOCK_STM32_PLL_SRC_HSI`	HSI
`CONFIG_CLOCK_STM32_PLL_SRC_HSE`	HSE
`CONFIG_CLOCK_STM32_PLL_PREDIV`	PREDIV Prescaler
`CONFIG_CLOCK_STM32_PLL_PREDIV1`	PREDIV1 Prescaler
`CONFIG_CLOCK_STM32_PLL_MULTIPLIER`	PLL multiplier
`CONFIG_CLOCK_STM32_PLL_M_DIVISOR`	PLL divisor
`CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER`	PLL multiplier
`CONFIG_CLOCK_STM32_PLL_P_DIVISOR`	PLL P Divisor
`CONFIG_CLOCK_STM32_PLL_Q_DIVISOR`	PLL Q Divisor
`CONFIG_CLOCK_STM32_PLL_R_DIVISOR`	PLL R Divisor
`CONFIG_CLOCK_STM32_AHB_PRESCALER`	AHB prescaler
`CONFIG_CLOCK_STM32_APB1_PRESCALER`	APB1 prescaler
`CONFIG_CLOCK_STM32_APB2_PRESCALER`	APB2 prescaler
`CONFIG_CLOCK_CONTROL_STM32F10X`	STM32F10x Reset & Clock Control
`CONFIG_CLOCK_CONTROL_STM32F10X_DEVICE_INIT_PRIORITY`	Clock Control Device Priority
`CONFIG_CLOCK_STM32F10X_SYSCLK_SRC_HSI`	HSI
`CONFIG_CLOCK_STM32F10X_SYSCLK_SRC_HSE`	HSE
`CONFIG_CLOCK_STM32F10X_SYSCLK_SRC_PLL`	PLL
`CONFIG_CLOCK_STM32F10X_PLL_SRC_HSI`	HSI
`CONFIG_CLOCK_STM32F10X_PLL_SRC_HSE`	HSE
`CONFIG_CLOCK_STM32F10X_HSE_BYPASS`	HSE bypass
`CONFIG_CLOCK_STM32F10X_PLL_XTPRE`	HSE to PLL /2 prescaler
`CONFIG_CLOCK_STM32F10X_PLL_MULTIPLIER`	PLL multiplier
`CONFIG_CLOCK_STM32F10X_AHB_PRESCALER`	AHB prescaler
`CONFIG_CLOCK_STM32F10X_APB1_PRESCALER`	APB1 prescaler
`CONFIG_CLOCK_STM32F10X_APB2_PRESCALER`	APB2 prescaler
`CONFIG_CLOCK_CONTROL_STM32F10X_CONN_LINE`	STM32F107x Reset & Clock Control
`CONFIG_CLOCK_CONTROL_STM32F10X_CONN_LINE_DEVICE_INIT_PRIORITY`	Clock Control Device Priority
`CONFIG_CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSI`	HSI
`CONFIG_CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_HSE`	HSE
`CONFIG_CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK`	PLLCLK
`CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_SRC_HSI`	HSI
`CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1`	PREDIV1
`CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE`	HSE
`CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_PLL2CLK`	PLL2CLK
`CONFIG_CLOCK_STM32F10X_CONN_LINE_HSE_BYPASS`	HSE bypass
`CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1`	PREDIV1 Prescler
`CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER`	PLL multiplier
`CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL2_MULTIPLIER`	PLL2 multiplier
`CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV2`	PREDIV2 Prescler
`CONFIG_CLOCK_STM32F10X_CONN_LINE_AHB_PRESCALER`	AHB prescaler
`CONFIG_CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER`	APB1 prescaler
`CONFIG_CLOCK_STM32F10X_CONN_LINE_APB2_PRESCALER`	APB2 prescaler
`CONFIG_CLOCK_CONTROL_STM32F4X`	STM32F4X Reset & Clock Control
`CONFIG_CLOCK_CONTROL_STM32F4X_DEVICE_INIT_PRIORITY`	Clock Control Device Priority
`CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_HSI`	HSI
`CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_HSE`	HSE
`CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL`	PLL
`CONFIG_CLOCK_STM32F4X_PLL_SRC_HSI`	HSI
`CONFIG_CLOCK_STM32F4X_PLL_SRC_HSE`	HSE
`CONFIG_CLOCK_STM32F4X_HSE_BYPASS`	HSE bypass
`CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR`	Division factor for PLL VCO input clock
`CONFIG_CLOCK_STM32F4X_PLLN_MULTIPLIER`	Multiplier factor for PLL VCO output clock
`CONFIG_CLOCK_STM32F4X_PLLP_DIV_FACTOR`	PLL division factor for main system clock
`CONFIG_CLOCK_STM32F4X_PLLQ_DIV_FACTOR`	Division factor for OTG FS, SDIO and RNG clocks
`CONFIG_CLOCK_STM32F4X_AHB_PRESCALER`	AHB prescaler
`CONFIG_CLOCK_STM32F4X_APB1_PRESCALER`	APB1 low speed clock prescaler
`CONFIG_CLOCK_STM32F4X_APB2_PRESCALER`	APB2 high speed clock prescaler
`CONFIG_CLOCK_CONTROL_BEETLE`	BEETLE Clock Control
`CONFIG_CLOCK_CONTROL_BEETLE_DEVICE_INIT_PRIORITY`	Clock Control Device Priority
`CONFIG_ARM_CLOCK_CONTROL_DEV_NAME`	Clock Config Device name
`CONFIG_CLOCK_CONTROL_BEETLE_ENABLE_PLL`	Enable PLL on Beetle
`CONFIG_IPM`	IPM drivers
`CONFIG_IPM_QUARK_SE`	Quark SE IPM driver
`CONFIG_IPM_QUARK_SE_MASTER`	Quark SE IPM master controller
`CONFIG_AIO_COMPARATOR`	AIO/Comparator Configuration
`CONFIG_AIO_COMPARATOR_QMSI`	Enable QMSI AIO/comparator driver
`CONFIG_AIO_COMPARATOR_0_NAME`	Device name for AIO/comparator
`CONFIG_AIO_COMPARATOR_0_IRQ_PRI`	IRQ Priority for AIO/comparator
`CONFIG_FLASH`	flash hardware support
`CONFIG_SPI_FLASH_W25QXXDV`	SPI NOR Flash Winbond W25QXXDV
`CONFIG_SPI_FLASH_W25QXXDV_SPI_NAME`	spi controller device name
`CONFIG_SPI_FLASH_W25QXXDV_DRV_NAME`	spi flash device name
`CONFIG_SPI_FLASH_W25QXXDV_INIT_PRIORITY`
`CONFIG_SPI_FLASH_W25QXXDV_SPI_FREQ_0`	SPI system frequency
`CONFIG_SPI_FLASH_W25QXXDV_SPI_SLAVE`	SPI slave linked to spi flash
`CONFIG_SPI_FLASH_W25QXXDV_FLASH_SIZE`	flash size in bytes
`CONFIG_SPI_FLASH_W25QXXDV_MAX_DATA_LEN`
`CONFIG_SOC_FLASH_QMSI`	QMSI flash driver
`CONFIG_SOC_FLASH_QMSI_DEV_NAME`	QMSI flash device name
`CONFIG_SOC_FLASH_QMSI_CLK_COUNT_US`	system clk count per microsecond
`CONFIG_SOC_FLASH_QMSI_WAIT_STATES`	The number of flash wait states
`CONFIG_SOC_FLASH_QMSI_SYS_SIZE`	SOC system flash size
`CONFIG_SOC_FLASH_QMSI_API_REENTRANCY`	flash driver API reentrancy for QMSI shim driver
`CONFIG_SOC_FLASH_NRF5`	Nordic Semiconductor nRF5X flash driver
`CONFIG_SOC_FLASH_NRF5_DEV_NAME`	Nordic nRF5X flash device name
`CONFIG_SOC_FLASH_MCUX`	MCUX flash shim driver
`CONFIG_SOC_FLASH_MCUX_DEV_NAME`	MCUX flash device name
`CONFIG_SOC_FLASH_STM32`	STM32 flash driver
`CONFIG_SOC_FLASH_STM32_DEV_NAME`	STM32 flash device name
`CONFIG_SENSOR`	Sensor Drivers
`CONFIG_SYS_LOG_SENSOR_LEVEL`	Sensor Log level
`CONFIG_SENSOR_INIT_PRIORITY`	Sensor init priority
`CONFIG_AK8975`	AK8975 Magnetometer
`CONFIG_AK8975_NAME`	Driver name
`CONFIG_AK8975_I2C_ADDR`	I2C address
`CONFIG_AK8975_I2C_MASTER_DEV_NAME`	I2C master where AK8975 is connected
`CONFIG_MPU9150`	Enable MPU9180 support
`CONFIG_MPU9150_I2C_ADDR`	MPU9180 I2C address
`CONFIG_BMA280`	BMA280 Three Axis Accelerometer Family
`CONFIG_BMA280_CHIP_BMA280`	BMA280
`CONFIG_BMA280_CHIP_BMC150_ACCEL`	BMC150_ACCEL
`CONFIG_BMA280_NAME`	Driver name
`CONFIG_BMA280_I2C_ADDR`	BMA280 I2C address
`CONFIG_BMA280_I2C_MASTER_DEV_NAME`	I2C master device name
`CONFIG_BMA280_TRIGGER_NONE`	No trigger
`CONFIG_BMA280_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_BMA280_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_BMA280_TRIGGER`
`CONFIG_BMA280_GPIO_DEV_NAME`	GPIO device
`CONFIG_BMA280_GPIO_PIN_NUM`	Interrupt GPIO pin number
`CONFIG_BMA280_THREAD_PRIORITY`	Thread priority
`CONFIG_BMA280_THREAD_STACK_SIZE`	Thread stack size
`CONFIG_BMA280_PMU_RANGE_2G`	+/-2g
`CONFIG_BMA280_PMU_RANGE_4G`	+/-4g
`CONFIG_BMA280_PMU_RANGE_8G`	+/-8g
`CONFIG_BMA280_PMU_RANGE_16G`	+/-16g
`CONFIG_BMA280_PMU_BW_1`	7.81Hz
`CONFIG_BMA280_PMU_BW_2`	15.63HZ
`CONFIG_BMA280_PMU_BW_3`	31.25Hz
`CONFIG_BMA280_PMU_BW_4`	62.5Hz
`CONFIG_BMA280_PMU_BW_5`	125Hz
`CONFIG_BMA280_PMU_BW_6`	250HZ
`CONFIG_BMA280_PMU_BW_7`	500Hz
`CONFIG_BMA280_PMU_BW_8`	unfiltered
`CONFIG_BMC150_MAGN`	BMC150_MAGN I2C Magnetometer Chip
`CONFIG_BMC150_MAGN_DEV_NAME`	BMC150_MAGN device name
`CONFIG_BMC150_MAGN_I2C_ADDR`	BMC150_MAGN I2C slave address
`CONFIG_BMC150_MAGN_I2C_MASTER_DEV_NAME`	I2C master where BMC150_MAGN is connected
`CONFIG_BMC150_MAGN_PRESET_LOW_POWER`	Low power (3, 3, 10)
`CONFIG_BMC150_MAGN_PRESET_REGULAR`	Regular (9, 15, 10)
`CONFIG_BMC150_MAGN_PRESET_ENHANCED_REGULAR`	Enhanced regular (15, 27, 10)
`CONFIG_BMC150_MAGN_PRESET_HIGH_ACCURACY`	High accuracy (47, 83, 20)
`CONFIG_BMC150_MAGN_SAMPLING_RATE_RUNTIME`	Enable dynamic sampling rate
`CONFIG_BMC150_MAGN_SAMPLING_REP_XY`	Enable dynamic XY oversampling
`CONFIG_BMC150_MAGN_SAMPLING_REP_Z`	Enable dynamic Z oversampling
`CONFIG_BMC150_MAGN_TRIGGER`	Enable triggers
`CONFIG_BMC150_MAGN_TRIGGER_THREAD_STACK`	Thread stack size
`CONFIG_BMC150_MAGN_TRIGGER_DRDY`	Enable data ready trigger
`CONFIG_BMC150_MAGN_GPIO_DRDY_DEV_NAME`	GPIO device where BMC150_MAGN data ready interrupt is connected
`CONFIG_BMC150_MAGN_GPIO_DRDY_INT_PIN`	GPIO pin number for the data ready interrupt pin
`CONFIG_BME280`	BME280/BMP280 sensor
`CONFIG_BME280_DEV_NAME`	BME280 device name
`CONFIG_BME280_I2C_ADDR`	BME280 I2C slave address
`CONFIG_BME280_I2C_MASTER_DEV_NAME`	I2C master where BME280 is connected
`CONFIG_BME280_TEMP_OVER_1X`	x1
`CONFIG_BME280_TEMP_OVER_2X`	x2
`CONFIG_BME280_TEMP_OVER_4X`	x4
`CONFIG_BME280_TEMP_OVER_8X`	x8
`CONFIG_BME280_TEMP_OVER_16X`	x16
`CONFIG_BME280_PRESS_OVER_1X`	x1
`CONFIG_BME280_PRESS_OVER_2X`	x2
`CONFIG_BME280_PRESS_OVER_4X`	x4
`CONFIG_BME280_PRESS_OVER_8X`	x8
`CONFIG_BME280_PRESS_OVER_16X`	x16
`CONFIG_BME280_HUMIDITY_OVER_1X`	x1
`CONFIG_BME280_HUMIDITY_OVER_2X`	x2
`CONFIG_BME280_HUMIDITY_OVER_4X`	x4
`CONFIG_BME280_HUMIDITY_OVER_8X`	x8
`CONFIG_BME280_HUMIDITY_OVER_16X`	x16
`CONFIG_BME280_STANDBY_05MS`	0.5ms
`CONFIG_BME280_STANDBY_62MS`	62.5ms
`CONFIG_BME280_STANDBY_125MS`	125ms
`CONFIG_BME280_STANDBY_250MS`	250ms
`CONFIG_BME280_STANDBY_500MS`	500ms
`CONFIG_BME280_STANDBY_1000MS`	1000ms
`CONFIG_BME280_STANDBY_2000MS`	2000ms BMP280 / 10ms BME280
`CONFIG_BME280_STANDBY_4000MS`	4000ms BMP280 / 20ms BME280
`CONFIG_BME280_FILTER_OFF`	filter off
`CONFIG_BME280_FILTER_2`	2
`CONFIG_BME280_FILTER_4`	4
`CONFIG_BME280_FILTER_8`	8
`CONFIG_BME280_FILTER_16`	16
`CONFIG_BMG160`	Bosch BMG160 gyroscope support
`CONFIG_BMG160_DRV_NAME`	Driver’s name
`CONFIG_BMG160_I2C_PORT_NAME`	I2C master controller port name
`CONFIG_BMG160_I2C_ADDR`	BMG160 I2C address
`CONFIG_BMG160_I2C_SPEED_STANDARD`	Standard
`CONFIG_BMG160_I2C_SPEED_FAST`	Fast
`CONFIG_BMG160_TRIGGER_NONE`	No trigger
`CONFIG_BMG160_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_BMG160_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_BMG160_TRIGGER`
`CONFIG_BMG160_THREAD_PRIORITY`	Own thread priority
`CONFIG_BMG160_THREAD_STACK_SIZE`	Own thread stack size
`CONFIG_BMG160_GPIO_PORT_NAME`	GPIO controller port name
`CONFIG_BMG160_INT_PIN`	BMG160 INT PIN
`CONFIG_BMG160_RANGE_RUNTIME`	Set at runtime.
`CONFIG_BMG160_RANGE_2000DPS`	2000 DPS
`CONFIG_BMG160_RANGE_1000DPS`	1000 DPS
`CONFIG_BMG160_RANGE_500DPS`	500 DPS
`CONFIG_BMG160_RANGE_250DPS`	250 DPS
`CONFIG_BMG160_RANGE_125DPS`	125 DPS
`CONFIG_BMG160_ODR_RUNTIME`	Set at runtime.
`CONFIG_BMG160_ODR_100`	100 Hz
`CONFIG_BMG160_ODR_200`	200 Hz
`CONFIG_BMG160_ODR_400`	400 Hz
`CONFIG_BMG160_ODR_1000`	1000 Hz
`CONFIG_BMG160_ODR_2000`	2000 Hz
`CONFIG_BMI160`	Bosch BMI160 inertial measurement unit
`CONFIG_BMI160_NAME`	Driver’s name
`CONFIG_BMI160_SPI_PORT_NAME`	SPI master controller port name
`CONFIG_BMI160_SLAVE`	BMI160 SPI slave select pin
`CONFIG_BMI160_SPI_BUS_FREQ`	BMI160 SPI bus speed in Hz
`CONFIG_BMI160_TRIGGER_NONE`	No trigger
`CONFIG_BMI160_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_BMI160_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_BMI160_TRIGGER`
`CONFIG_BMI160_THREAD_PRIORITY`	Own thread priority
`CONFIG_BMI160_THREAD_STACK_SIZE`	Own thread stack size
`CONFIG_BMI160_GPIO_DEV_NAME`	Gpio device
`CONFIG_BMI160_GPIO_PIN_NUM`	Interrupt GPIO pin number
`CONFIG_BMI160_ACCEL_PMU_RUNTIME`	Set at runtime.
`CONFIG_BMI160_ACCEL_PMU_SUSPEND`	suspended/not used
`CONFIG_BMI160_ACCEL_PMU_NORMAL`	normal
`CONFIG_BMI160_ACCEL_PMU_LOW_POWER`	low power
`CONFIG_BMI160_ACCEL_RANGE_RUNTIME`	Set at runtime.
`CONFIG_BMI160_ACCEL_RANGE_2G`	2G
`CONFIG_BMI160_ACCEL_RANGE_4G`	4G
`CONFIG_BMI160_ACCEL_RANGE_8G`	8G
`CONFIG_BMI160_ACCEL_RANGE_16G`	16G
`CONFIG_BMI160_ACCEL_ODR_RUNTIME`	Set at runtime.
`CONFIG_BMI160_ACCEL_ODR_25_32`	0.78 Hz
`CONFIG_BMI160_ACCEL_ODR_25_16`	1.56 Hz
`CONFIG_BMI160_ACCEL_ODR_25_8`	3.125 Hz
`CONFIG_BMI160_ACCEL_ODR_25_4`	6.25 Hz
`CONFIG_BMI160_ACCEL_ODR_25_2`	12.5 Hz
`CONFIG_BMI160_ACCEL_ODR_25`	25 Hz
`CONFIG_BMI160_ACCEL_ODR_50`	50 Hz
`CONFIG_BMI160_ACCEL_ODR_100`	100 Hz
`CONFIG_BMI160_ACCEL_ODR_200`	200 Hz
`CONFIG_BMI160_ACCEL_ODR_400`	400 Hz
`CONFIG_BMI160_ACCEL_ODR_800`	800 Hz
`CONFIG_BMI160_ACCEL_ODR_1600`	1600 Hz
`CONFIG_BMI160_GYRO_PMU_RUNTIME`	Set at runtime.
`CONFIG_BMI160_GYRO_PMU_SUSPEND`	suspended/not used
`CONFIG_BMI160_GYRO_PMU_NORMAL`	normal
`CONFIG_BMI160_GYRO_PMU_FAST_STARTUP`	fast start-up
`CONFIG_BMI160_GYRO_RANGE_RUNTIME`	Set at runtime.
`CONFIG_BMI160_GYRO_RANGE_2000DPS`	2000 DPS
`CONFIG_BMI160_GYRO_RANGE_1000DPS`	1000 DPS
`CONFIG_BMI160_GYRO_RANGE_500DPS`	500 DPS
`CONFIG_BMI160_GYRO_RANGE_250DPS`	250 DPS
`CONFIG_BMI160_GYRO_RANGE_125DPS`	125 DPS
`CONFIG_BMI160_GYRO_ODR_RUNTIME`	Set at runtime.
`CONFIG_BMI160_GYRO_ODR_25`	25 Hz
`CONFIG_BMI160_GYRO_ODR_50`	50 Hz
`CONFIG_BMI160_GYRO_ODR_100`	100 Hz
`CONFIG_BMI160_GYRO_ODR_200`	200 Hz
`CONFIG_BMI160_GYRO_ODR_400`	400 Hz
`CONFIG_BMI160_GYRO_ODR_800`	800 Hz
`CONFIG_BMI160_GYRO_ODR_1600`	1600 Hz
`CONFIG_BMI160_GYRO_ODR_3200`	3200 Hz
`CONFIG_DHT`	DHT Temperature and Humidity Sensor
`CONFIG_DHT_CHIP_DHT11`	DHT11
`CONFIG_DHT_CHIP_DHT22`	DHT22
`CONFIG_DHT_NAME`	Driver name
`CONFIG_DHT_GPIO_DEV_NAME`	GPIO device
`CONFIG_DHT_GPIO_PIN_NUM`	Interrupt GPIO pin number
`CONFIG_FXOS8700`	FXOS8700 accelerometer/magnetometer driver
`CONFIG_FXOS8700_NAME`	Device name
`CONFIG_FXOS8700_I2C_NAME`	I2C device name
`CONFIG_FXOS8700_I2C_ADDRESS`	I2C address
`CONFIG_FXOS8700_WHOAMI`	WHOAMI value
`CONFIG_FXOS8700_MODE_ACCEL`	Accelerometer-only mode
`CONFIG_FXOS8700_MODE_MAGN`	Magnetometer-only mode
`CONFIG_FXOS8700_MODE_HYBRID`	Hybrid (accel+mag) mode
`CONFIG_FXOS8700_RANGE_8G`	8g (0.976 mg/LSB)
`CONFIG_FXOS8700_RANGE_4G`	4g (0.488 mg/LSB)
`CONFIG_FXOS8700_RANGE_2G`	2g (0.244 mg/LSB)
`CONFIG_FXOS8700_TRIGGER_NONE`	No trigger
`CONFIG_FXOS8700_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_FXOS8700_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_FXOS8700_TRIGGER`
`CONFIG_FXOS8700_GPIO_NAME`	GPIO device name
`CONFIG_FXOS8700_GPIO_PIN`	GPIO pin
`CONFIG_FXOS8700_DRDY_INT1`	Data ready interrupt to INT1 pin
`CONFIG_FXOS8700_THREAD_PRIORITY`	Own thread priority
`CONFIG_FXOS8700_THREAD_STACK_SIZE`	Own thread stack size
`CONFIG_FXOS8700_PULSE`	Pulse detection
`CONFIG_FXOS8700_PULSE_INT1`	Pulse interrupt to INT1 pin
`CONFIG_FXOS8700_PULSE_CFG`	Pulse configuration register
`CONFIG_FXOS8700_PULSE_THSX`	Pulse X-axis threshold
`CONFIG_FXOS8700_PULSE_THSY`	Pulse Y-axis threshold
`CONFIG_FXOS8700_PULSE_THSZ`	Pulse Z-axis threshold
`CONFIG_FXOS8700_PULSE_TMLT`	Pulse time limit
`CONFIG_FXOS8700_PULSE_LTCY`	Pulse latency
`CONFIG_FXOS8700_PULSE_WIND`	Pulse window
`CONFIG_HDC1008`	HDC1008 Temperature and Humidity Sensor
`CONFIG_HDC1008_NAME`	Driver name
`CONFIG_HDC1008_I2C_ADDR`	I2C Address for HDC1008
`CONFIG_HDC1008_I2C_MASTER_DEV_NAME`	I2C master where HDC1008 is connected
`CONFIG_HDC1008_GPIO_DEV_NAME`	GPIO device
`CONFIG_HDC1008_GPIO_PIN_NUM`	Interrupt GPIO pin number
`CONFIG_HMC5883L`	HMC5883L magnetometer
`CONFIG_HMC5883L_NAME`	Driver name
`CONFIG_HMC5883L_I2C_MASTER_DEV_NAME`	I2C master where HMC5883L is connected
`CONFIG_HMC5883L_TRIGGER_NONE`	No trigger
`CONFIG_HMC5883L_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_HMC5883L_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_HMC5883L_TRIGGER`
`CONFIG_HMC5883L_GPIO_DEV_NAME`	GPIO device
`CONFIG_HMC5883L_GPIO_PIN_NUM`	Interrupt GPIO pin number
`CONFIG_HMC5883L_THREAD_PRIORITY`	Thread priority
`CONFIG_HMC5883L_THREAD_STACK_SIZE`	Thread stack size
`CONFIG_HMC5883L_ODR`	Output data rate
`CONFIG_HMC5883L_FS`	Full-scale range
`CONFIG_HP206C`	HopeRF HP206C precision barometer and altimeter sensor
`CONFIG_HP206C_DRV_NAME`	Driver’s name
`CONFIG_HP206C_I2C_PORT_NAME`	I2C master controller port name
`CONFIG_HP206C_OSR_RUNTIME`	Oversampling rate set at runtime
`CONFIG_HP206C_OSR`	Oversampling rate
`CONFIG_HP206C_ALT_OFFSET_RUNTIME`	Altitude offset set at runtime
`CONFIG_HP206C_ALT_OFFSET`	Altitude offset (in cm)
`CONFIG_HTS221`	HTS221 temperature and humidity sensor
`CONFIG_HTS221_NAME`	Driver name
`CONFIG_HTS221_I2C_MASTER_DEV_NAME`	I2C master where HTS221 is connected
`CONFIG_HTS221_TRIGGER_NONE`	No trigger
`CONFIG_HTS221_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_HTS221_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_HTS221_TRIGGER`
`CONFIG_HTS221_GPIO_DEV_NAME`	GPIO device
`CONFIG_HTS221_GPIO_PIN_NUM`	Interrupt GPIO pin number
`CONFIG_HTS221_THREAD_PRIORITY`	Thread priority
`CONFIG_HTS221_THREAD_STACK_SIZE`	Thread stack size
`CONFIG_HTS221_ODR`	Output data rate
`CONFIG_ISL29035`	ISL29035 light sensor
`CONFIG_ISL29035_NAME`	Driver name
`CONFIG_ISL29035_I2C_MASTER_DEV_NAME`	I2C Master
`CONFIG_ISL29035_THREAD_PRIORITY`	Thread priority
`CONFIG_ISL29035_LUX_RANGE_1K`	1000
`CONFIG_ISL29035_LUX_RANGE_4K`	4000
`CONFIG_ISL29035_LUX_RANGE_16K`	16000
`CONFIG_ISL29035_LUX_RANGE_64K`	64000
`CONFIG_ISL29035_INTEGRATION_TIME_26`	0.0256 ms
`CONFIG_ISL29035_INTEGRATION_TIME_410`	0.41 ms
`CONFIG_ISL29035_INTEGRATION_TIME_6500`	6.5 ms
`CONFIG_ISL29035_INTEGRATION_TIME_105K`	105 ms
`CONFIG_ISL29035_MODE_ALS`	ambient light
`CONFIG_ISL29035_MODE_IR`	infrared
`CONFIG_ISL29035_TRIGGER_NONE`	No trigger
`CONFIG_ISL29035_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_ISL29035_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_ISL29035_TRIGGER`
`CONFIG_ISL29035_GPIO_DEV_NAME`	GPIO device
`CONFIG_ISL29035_GPIO_PIN_NUM`	GPIO pin number
`CONFIG_ISL29035_THREAD_STACK_SIZE`	Thread stack size
`CONFIG_ISL29035_INT_PERSIST_1`	1
`CONFIG_ISL29035_INT_PERSIST_4`	4
`CONFIG_ISL29035_INT_PERSIST_8`	8
`CONFIG_ISL29035_INT_PERSIST_16`	16
`CONFIG_LIS3DH`	LIS3DH Three Axis Accelerometer
`CONFIG_LIS3DH_NAME`	Driver name
`CONFIG_LIS3DH_I2C_ADDR`	LIS3DH I2C address
`CONFIG_LIS3DH_I2C_MASTER_DEV_NAME`	I2C master where LIS3DH is connected
`CONFIG_LIS3DH_TRIGGER_NONE`	No trigger
`CONFIG_LIS3DH_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_LIS3DH_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_LIS3DH_TRIGGER`
`CONFIG_LIS3DH_GPIO_DEV_NAME`	GPIO device
`CONFIG_LIS3DH_GPIO_PIN_NUM`	Interrupt GPIO pin number
`CONFIG_LIS3DH_THREAD_PRIORITY`	Thread priority
`CONFIG_LIS3DH_THREAD_STACK_SIZE`	Thread stack size
`CONFIG_LIS3DH_ACCEL_RANGE_2G`	+/-2g
`CONFIG_LIS3DH_ACCEL_RANGE_4G`	+/-4g
`CONFIG_LIS3DH_ACCEL_RANGE_8G`	+/-8g
`CONFIG_LIS3DH_ACCEL_RANGE_16G`	+/-16g
`CONFIG_LIS3DH_POWER_MODE_NORMAL`	normal
`CONFIG_LIS3DH_POWER_MODE_LOW`	low
`CONFIG_LIS3DH_ODR_1`	1Hz
`CONFIG_LIS3DH_ODR_2`	10Hz
`CONFIG_LIS3DH_ODR_3`	25Hz
`CONFIG_LIS3DH_ODR_4`	50Hz
`CONFIG_LIS3DH_ODR_5`	100Hz
`CONFIG_LIS3DH_ODR_6`	200Hz
`CONFIG_LIS3DH_ODR_7`	400Hz
`CONFIG_LIS3DH_ODR_8`	1.6KHz
`CONFIG_LIS3DH_ODR_9_NORMAL`	1.25KHz
`CONFIG_LIS3DH_ODR_9_LOW`	5KHz
`CONFIG_LIS3MDL`	LIS3MDL magnetometer
`CONFIG_LIS3MDL_NAME`	Driver name
`CONFIG_LIS3MDL_I2C_ADDR`	I2C address
`CONFIG_LIS3MDL_I2C_MASTER_DEV_NAME`	I2C master where LIS3MDL is connected
`CONFIG_LIS3MDL_TRIGGER_NONE`	No trigger
`CONFIG_LIS3MDL_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_LIS3MDL_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_LIS3MDL_TRIGGER`
`CONFIG_LIS3MDL_GPIO_DEV_NAME`	GPIO device
`CONFIG_LIS3MDL_GPIO_PIN_NUM`	Interrupt GPIO pin number
`CONFIG_LIS3MDL_THREAD_PRIORITY`	Thread priority
`CONFIG_LIS3MDL_THREAD_STACK_SIZE`	Thread stack size
`CONFIG_LIS3MDL_ODR`	Output data rate
`CONFIG_LIS3MDL_FS`	Full-scale range
`CONFIG_LPS25HB`	LPS25HB pressure and temperature
`CONFIG_LPS25HB_DEV_NAME`	Device name
`CONFIG_LPS25HB_I2C_ADDR`	I2C address
`CONFIG_LPS25HB_I2C_MASTER_DEV_NAME`	I2C master where LPS25HB is connected
`CONFIG_LPS25HB_SAMPLING_RATE`	Output data rate
`CONFIG_LSM6DS0`	LSM6DS0 I2C accelerometer and gyroscope Chip
`CONFIG_LSM6DS0_DEV_NAME`	LSM6DS0 device name
`CONFIG_LSM6DS0_I2C_ADDR`	LSM6DS0 I2C address
`CONFIG_LSM6DS0_I2C_MASTER_DEV_NAME`	I2C master where LSM6DS0 chip is connected
`CONFIG_LSM6DS0_ACCEL_ENABLE_X_AXIS`	Enable accelerometer X axis
`CONFIG_LSM6DS0_ACCEL_ENABLE_Y_AXIS`	Enable accelerometer Y axis
`CONFIG_LSM6DS0_ACCEL_ENABLE_Z_AXIS`	Enable accelerometer Z axis
`CONFIG_LSM6DS0_GYRO_ENABLE_X_AXIS`	Enable gyroscope X axis
`CONFIG_LSM6DS0_GYRO_ENABLE_Y_AXIS`	Enable gyroscope Y axis
`CONFIG_LSM6DS0_GYRO_ENABLE_Z_AXIS`	Enable gyroscope Z axis
`CONFIG_LSM6DS0_ENABLE_TEMP`	Enable temperature
`CONFIG_LSM6DS0_GYRO_FULLSCALE`	Gyroscope full-scale range
`CONFIG_LSM6DS0_GYRO_SAMPLING_RATE`	Output data rate
`CONFIG_LSM6DS0_ACCEL_FULLSCALE`	Accelerometer full-scale range
`CONFIG_LSM6DS0_ACCEL_SAMPLING_RATE`	Output data rate
`CONFIG_LSM9DS0_GYRO`	LSM9DS0 I2C gyroscope Chip
`CONFIG_LSM9DS0_GYRO_DEV_NAME`	LSM9DS0_GYRO device name
`CONFIG_LSM9DS0_GYRO_I2C_ADDR`	LSM9DS0_GYRO I2C slave address
`CONFIG_LSM9DS0_GYRO_I2C_MASTER_DEV_NAME`	I2C master where LSM9DS0 gyroscope is connected
`CONFIG_LSM9DS0_GYRO_FULLSCALE_245`	245 DPS
`CONFIG_LSM9DS0_GYRO_FULLSCALE_500`	500 DPS
`CONFIG_LSM9DS0_GYRO_FULLSCALE_2000`	2000 DPS
`CONFIG_LSM9DS0_GYRO_FULLSCALE_RUNTIME`	Enable dynamic full-scale
`CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_95`	95 Hz
`CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_190`	190 Hz
`CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_380`	380 Hz
`CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_760`	760 Hz
`CONFIG_LSM9DS0_GYRO_SAMPLING_RATE_RUNTIME`	Enable dynamic sampling rate
`CONFIG_LSM9DS0_GYRO_TRIGGERS`	Enable triggers
`CONFIG_LSM9DS0_GYRO_THREAD_STACK_SIZE`	Thread stack size
`CONFIG_LSM9DS0_GYRO_TRIGGER_DRDY`	Enable data ready trigger
`CONFIG_LSM9DS0_GYRO_GPIO_DRDY_DEV_NAME`	GPIO device where LSM9DS0_GYRO data ready interrupt is connected
`CONFIG_LSM9DS0_GYRO_GPIO_DRDY_INT_PIN`	GPIO pin number for the data ready interrupt pin
`CONFIG_LSM9DS0_MFD`	LSM9DS0 I2C accelerometer, magnetometer and temperature sensor chip
`CONFIG_LSM9DS0_MFD_DEV_NAME`	LSM9DS0_MFD device name
`CONFIG_LSM9DS0_MFD_I2C_ADDR`	LSM9DS0_MFD I2C slave address
`CONFIG_LSM9DS0_MFD_I2C_MASTER_DEV_NAME`	I2C master where LSM9DS0 gyroscope is connected
`CONFIG_LSM9DS0_MFD_ACCEL_ENABLE`	Enable accelerometer
`CONFIG_LSM9DS0_MFD_MAGN_ENABLE`	Enable magnetometer
`CONFIG_LSM9DS0_MFD_TEMP_ENABLE`	Enable temperature sensor
`CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_0`	0 Hz (power down)
`CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_3_125`	3.125 Hz
`CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_6_25`	6.25 Hz
`CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_12_5`	12.5 Hz
`CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_25`	25 Hz
`CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_50`	50 Hz
`CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_100`	100 Hz
`CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_200`	200 Hz
`CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_400`	400 Hz
`CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_800`	800 Hz
`CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_1600`	1600 Hz
`CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_RUNTIME`	Enable dynamic sampling rate for accelerometer
`CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_2`	2G
`CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_4`	4G
`CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_6`	6G
`CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_8`	8G
`CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_16`	16G
`CONFIG_LSM9DS0_MFD_ACCEL_FULL_SCALE_RUNTIME`	Enable dynamic full-scale for accelerometer
`CONFIG_LSM9DS0_MFD_ACCEL_ENABLE_X`	Enable accelerometer X axis
`CONFIG_LSM9DS0_MFD_ACCEL_ENABLE_Y`	Enable accelerometer Y axis
`CONFIG_LSM9DS0_MFD_ACCEL_ENABLE_Z`	Enable accelerometer Z axis
`CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_3_125`	3.125 Hz
`CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_6_25`	6.25 Hz
`CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_12_5`	12.5 Hz
`CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_25`	25 Hz
`CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_50`	50 Hz
`CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_100`	100 Hz
`CONFIG_LSM9DS0_MFD_MAGN_SAMPLING_RATE_RUNTIME`	Enable dynamic sampling rate for magnetometer
`CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_2`	2 Gauss
`CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_4`	4 Gauss
`CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_8`	8 Gauss
`CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_12`	12 Gauss
`CONFIG_LSM9DS0_MFD_MAGN_FULL_SCALE_RUNTIME`	Enable dynamic full-scale for magnetometer
`CONFIG_MAX44009`	MAX44009 Light Sensor
`CONFIG_MAX44009_DRV_NAME`	Driver name
`CONFIG_MAX44009_I2C_ADDR`	MAX44009 I2C address
`CONFIG_MAX44009_I2C_DEV_NAME`	I2C master where MAX44009 is connected
`CONFIG_MCP9808`	MCP9808 temperature sensor
`CONFIG_MCP9808_DEV_NAME`	MCP9808 device name
`CONFIG_MCP9808_I2C_ADDR`	MCP9808 I2C slave address
`CONFIG_MCP9808_I2C_DEV_NAME`	I2C master where MCP9808 is connected
`CONFIG_MCP9808_TRIGGER_NONE`	No trigger
`CONFIG_MCP9808_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_MCP9808_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_MCP9808_TRIGGER`
`CONFIG_MCP9808_GPIO_CONTROLLER`	GPIO controller for MCP9808 interrupt
`CONFIG_MCP9808_GPIO_PIN`	GPIO pin for MCP9808 interrupt
`CONFIG_MCP9808_THREAD_STACK_SIZE`	Sensor delayed work thread stack size
`CONFIG_MCP9808_THREAD_PRIORITY`	MCP9808 thread priority
`CONFIG_MPU6050`	MPU6050 Six-Axis Motion Tracking Device
`CONFIG_MPU6050_NAME`	Driver name
`CONFIG_MPU6050_I2C_ADDR`	I2C address
`CONFIG_MPU6050_I2C_MASTER_DEV_NAME`	I2C master where MPU6050 is connected
`CONFIG_MPU6050_TRIGGER_NONE`	No trigger
`CONFIG_MPU6050_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_MPU6050_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_MPU6050_TRIGGER`
`CONFIG_MPU6050_GPIO_DEV_NAME`	GPIO device
`CONFIG_MPU6050_GPIO_PIN_NUM`	Interrupt GPIO pin number
`CONFIG_MPU6050_THREAD_PRIORITY`	Thread priority
`CONFIG_MPU6050_THREAD_STACK_SIZE`	Thread stack size
`CONFIG_MPU6050_ACCEL_FS`	Accelerometer full-scale range
`CONFIG_MPU6050_GYRO_FS`	Gyroscope full-scale range
`CONFIG_TEMP_NRF5`	nRF5 Temperature Sensor
`CONFIG_TEMP_NRF5_NAME`	Driver name
`CONFIG_TEMP_NRF5_PRI`	TEMP interrupt priority
`CONFIG_SHT3XD`	SHT3xD Temperature and Humidity Sensor
`CONFIG_SHT3XD_NAME`	Driver name
`CONFIG_SHT3XD_I2C_ADDR`	SHT3XD I2C address
`CONFIG_SHT3XD_I2C_MASTER_DEV_NAME`	I2C master where SHT3xD is connected
`CONFIG_SHT3XD_TRIGGER_NONE`	No trigger
`CONFIG_SHT3XD_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_SHT3XD_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_SHT3XD_TRIGGER`
`CONFIG_SHT3XD_GPIO_DEV_NAME`	GPIO device
`CONFIG_SHT3XD_GPIO_PIN_NUM`	Interrupt GPIO pin number
`CONFIG_SHT3XD_THREAD_PRIORITY`	Thread priority
`CONFIG_SHT3XD_THREAD_STACK_SIZE`	Thread stack size
`CONFIG_SHT3XD_REPEATABILITY_LOW`	low
`CONFIG_SHT3XD_REPEATABILITY_MEDIUM`	medium
`CONFIG_SHT3XD_REPEATABILITY_HIGH`	high
`CONFIG_SHT3XD_MPS_05`	0.5
`CONFIG_SHT3XD_MPS_1`	1
`CONFIG_SHT3XD_MPS_2`	2
`CONFIG_SHT3XD_MPS_4`	4
`CONFIG_SHT3XD_MPS_10`	10
`CONFIG_SX9500`	SX9500 I2C SAR Proximity Chip
`CONFIG_SX9500_DEV_NAME`	SX9500 device name
`CONFIG_SX9500_I2C_ADDR`	SX9500 I2C slave address
`CONFIG_SX9500_I2C_DEV_NAME`	I2C master where SX9500 is connected
`CONFIG_SX9500_PROX_CHANNEL`	Proximity channel to use
`CONFIG_SX9500_TRIGGER_NONE`	No trigger
`CONFIG_SX9500_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_SX9500_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_SX9500_TRIGGER`
`CONFIG_SX9500_GPIO_CONTROLLER`	GPIO controller for SX9500 interrupt
`CONFIG_SX9500_GPIO_PIN`	GPIO pin for SX9500 interrupt
`CONFIG_SX9500_THREAD_STACK_SIZE`	Sensor delayed work thread stack size
`CONFIG_SX9500_THREAD_PRIORITY`	Thread priority
`CONFIG_TH02`	TH02 Temperature Sensor
`CONFIG_TH02_NAME`	Driver name
`CONFIG_TH02_I2C_MASTER_DEV_NAME`	I2C Master
`CONFIG_TMP007`	TMP007 Infrared Thermopile Sensor
`CONFIG_TMP007_NAME`	Driver name
`CONFIG_TMP007_I2C_ADDR`	I2C address for TMP006 Sensor
`CONFIG_TMP007_I2C_MASTER_DEV_NAME`	I2C master where TMP007 is connected
`CONFIG_TMP007_TRIGGER_NONE`	No trigger
`CONFIG_TMP007_TRIGGER_GLOBAL_THREAD`	Use global thread
`CONFIG_TMP007_TRIGGER_OWN_THREAD`	Use own thread
`CONFIG_TMP007_TRIGGER`
`CONFIG_TMP007_GPIO_DEV_NAME`	GPIO device
`CONFIG_TMP007_GPIO_PIN_NUM`	Interrupt GPIO pin number
`CONFIG_TMP007_THREAD_PRIORITY`	Thread priority
`CONFIG_TMP007_THREAD_STACK_SIZE`	Thread stack size
`CONFIG_TMP112`	TMP112 Temperature Sensor
`CONFIG_TMP112_NAME`	Driver name
`CONFIG_TMP112_I2C_ADDR`	I2C address for TMP112
`CONFIG_TMP112_I2C_MASTER_DEV_NAME`	I2C master where TMP112 is connected
`CONFIG_COUNTER`	Counter Drivers
`CONFIG_AON_COUNTER_QMSI`	AON counter driver
`CONFIG_AON_COUNTER_QMSI_DEV_NAME`	QMSI AON Counter Device Name
`CONFIG_AON_TIMER_QMSI`	AON periodic timer driver
`CONFIG_AON_TIMER_QMSI_DEV_NAME`	QMSI AON Timer Device Name
`CONFIG_AON_TIMER_IRQ_PRI`	Interrupt priority
`CONFIG_AON_API_REENTRANCY`	AON driver API reentrancy
`CONFIG_TIMER_TMR_CMSDK_APB`	ARM CMSDK (Cortex-M System Design Kit) Timer driver
`CONFIG_TIMER_TMR_CMSDK_APB_0`	Timer 0 driver
`CONFIG_TIMER_TMR_CMSDK_APB_0_DEV_NAME`	Timer 0 Device Name
`CONFIG_TIMER_TMR_CMSDK_APB_0_IRQ_PRI`	Interrupt Priority for Timer 0
`CONFIG_TIMER_TMR_CMSDK_APB_1`	Timer 1 driver
`CONFIG_TIMER_TMR_CMSDK_APB_1_DEV_NAME`	Timer 1 Device Name
`CONFIG_TIMER_TMR_CMSDK_APB_1_IRQ_PRI`	Interrupt Priority for Timer 1
`CONFIG_COUNTER_TMR_CMSDK_APB`	ARM CMSDK (Cortex-M System Design Kit) Counter driver
`CONFIG_COUNTER_TMR_CMSDK_APB_0`	Counter 0 driver
`CONFIG_COUNTER_TMR_CMSDK_APB_0_DEV_NAME`	Counter 0 Device Name
`CONFIG_COUNTER_TMR_CMSDK_APB_1`	Counter 1 driver
`CONFIG_COUNTER_TMR_CMSDK_APB_1_DEV_NAME`	Counter 1 Device Name
`CONFIG_TIMER_DTMR_CMSDK_APB`	ARM CMSDK (Cortex-M System Design Kit) DTMR Timer driver
`CONFIG_TIMER_DTMR_CMSDK_APB_0`	Timer 0 driver
`CONFIG_TIMER_DTMR_CMSDK_APB_0_DEV_NAME`	Timer 0 Device Name
`CONFIG_TIMER_DTMR_CMSDK_APB_0_IRQ_PRI`	Interrupt Priority for Timer 0
`CONFIG_COUNTER_DTMR_CMSDK_APB`	ARM CMSDK (Cortex-M System Design Kit) DTMR Counter driver
`CONFIG_COUNTER_DTMR_CMSDK_APB_0`	Counter 0 driver
`CONFIG_COUNTER_DTMR_CMSDK_APB_0_DEV_NAME`	Counter 0 Device Name
`CONFIG_DMA`	DMA driver Configuration
`CONFIG_DMA_QMSI`	Enable QMSI DMA driver
`CONFIG_DMA_0_NAME`	Device name for QMSI DMA Controller
`CONFIG_DMA_0_IRQ_PRI`	IRQ Priority for DMA
`CONFIG_USB`	USB
`CONFIG_USB_DW`	Designware USB Device Controller Driver
`CONFIG_USB_DW_IRQ_PRI`	DesignWare USB Driver Interrupt priority
`CONFIG_SYS_LOG_USB_DW_LEVEL`	DesignWare USB driver log level
`CONFIG_CRYPTO`	Crypto Drivers [EXPERIMENTAL]
`CONFIG_SYS_LOG_CRYPTO_LEVEL`	Crypto drivers log level
`CONFIG_CRYPTO_TINYCRYPT_SHIM`	Enable TinyCrypt shim driver [EXPERIMENTAL]
`CONFIG_CRYPTO_0_NAME`	Device name for TinyCrypt Pseudo device
`CONFIG_ATAES132A`	Atmel ATAES132A 32k AES Serial EEPROM support
`CONFIG_CRYPTO_INIT_PRIORITY`	Sensor init priority
`CONFIG_ATAES132A_DRV_NAME`	Driver’s name
`CONFIG_ATAES132A_I2C_PORT_NAME`	I2C master controller port name
`CONFIG_ATAES132A_I2C_ADDR`	ATAES132A I2C addess
`CONFIG_ATAES132A_I2C_SPEED_STANDARD`	Standard
`CONFIG_ATAES132A_I2C_SPEED_FAST`	Fast
`CONFIG_TEXT_SECTION_OFFSET`	TEXT section offset
`CONFIG_HAVE_CUSTOM_LINKER_SCRIPT`	Custom linker scripts provided
`CONFIG_CUSTOM_LINKER_SCRIPT`	Path to custom linker script
`CONFIG_CUSTOM_RODATA_LD`	Include custom-rodata.ld
`CONFIG_CUSTOM_RWDATA_LD`	Include custom-rwdata.ld
`CONFIG_CUSTOM_SECTIONS_LD`	Include custom-sections.ld
`CONFIG_LINK_WHOLE_ARCHIVE`	Allow linking with –whole-archive
`CONFIG_CROSS_COMPILE`	Cross-compiler tool prefix
`CONFIG_COMPILER_OPT`	Custom compiler options
`CONFIG_TOOLCHAIN_VARIANT`	Cross-compiler variant name
`CONFIG_CPLUSPLUS`	Enable C++ support for the application
`CONFIG_GDB_INFO`	Task-aware debugging with GDB
`CONFIG_KERNEL_BIN_NAME`	The kernel binary name
`CONFIG_DEBUG`	Build kernel with debugging enabled
`CONFIG_STACK_USAGE`	Generate stack usage information
`CONFIG_PRINTK`	Send printk() to console
`CONFIG_STDOUT_CONSOLE`	Send stdout to console
`CONFIG_EARLY_CONSOLE`	Send stdout at the earliest stage possible
`CONFIG_ASSERT`	Enable __ASSERT() macro
`CONFIG_ASSERT_LEVEL`	__ASSERT() level
`CONFIG_DEBUG_TRACING_KERNEL_OBJECTS`	Kernel object tracing (deprecated)
`CONFIG_OBJECT_TRACING`	Kernel object tracing
`CONFIG_OVERRIDE_FRAME_POINTER_DEFAULT`	Override compiler defaults for -fomit-frame-pointer
`CONFIG_OMIT_FRAME_POINTER`	Omit frame pointer
`CONFIG_PERFORMANCE_METRICS`	Enable performance metrics [EXPERIMENTAL]
`CONFIG_BOOT_TIME_MEASUREMENT`	Boot time measurements [EXPERIMENTAL]
`CONFIG_CPU_CLOCK_FREQ_MHZ`	CPU CLock Frequency in MHz
`CONFIG_IS_BOOTLOADER`	Act as a bootloader
`CONFIG_BOOTLOADER_SRAM_SIZE`	SRAM reserved for when Zephyr acts as a bootloader
`CONFIG_BOOTLOADER_KEXEC`	Boot using Linux kexec() system call
`CONFIG_BOOTLOADER_UNKNOWN`	Generic boot loader support
`CONFIG_BOOTLOADER_CONTEXT_RESTORE`	Boot loader has context restore support
`CONFIG_REBOOT`	Reboot functionality
`CONFIG_NEWLIB_LIBC`	Build with newlib c library
`CONFIG_NEWLIB_LIBC_FLOAT_PRINTF`	Build with newlib float printf
`CONFIG_NEWLIB_LIBC_FLOAT_SCANF`	Build with newlib float scanf
`CONFIG_JSON_LIBRARY`	Build JSON library
`CONFIG_FILE_SYSTEM`	File system support
`CONFIG_FILE_SYSTEM_SHELL`	Enable file system shell
`CONFIG_FILE_SYSTEM_FAT`	FAT file system support
`CONFIG_USB_DEVICE_STACK`	USB device stack
`CONFIG_SYS_LOG_USB_LEVEL`	Sets log level for the USB device stack
`CONFIG_USB_CDC_ACM`	USB CDC ACM Device Class Driver
`CONFIG_CDC_ACM_PORT_NAME`	CDC ACM class device driver port name
`CONFIG_SYS_LOG_USB_CDC_ACM_LEVEL`	USB CDC ACM device class driver log level
`CONFIG_USB_MASS_STORAGE`	USB Mass Storage Device Class Driver
`CONFIG_SYS_LOG_USB_MASS_STORAGE_LEVEL`	USB Mass Storage device class driver log level
`CONFIG_BLUETOOTH`	Bluetooth support
`CONFIG_BLUETOOTH_HCI`	HCI-based
`CONFIG_BLUETOOTH_CUSTOM`	Custom
`CONFIG_BLUETOOTH_CONTROLLER`	Bluetooth Controller
`CONFIG_BLUETOOTH_HCI_TX_STACK_SIZE`
`CONFIG_BLUETOOTH_HCI_RAW`	RAW HCI access
`CONFIG_BLUETOOTH_HCI_HOST`
`CONFIG_BLUETOOTH_RECV_IS_RX_THREAD`
`CONFIG_BLUETOOTH_HCI_CMD_COUNT`	Number of HCI command buffers
`CONFIG_BLUETOOTH_RX_BUF_COUNT`	Number of HCI RX buffers
`CONFIG_BLUETOOTH_RX_BUF_LEN`	Maximum supported HCI RX buffer length
`CONFIG_BLUETOOTH_UART_TO_HOST_DEV_NAME`	Device Name of UART Device to an external Bluetooth Host
`CONFIG_BLUETOOTH_INTERNAL_STORAGE`	Use an internal persistent storage handler
`CONFIG_BLUETOOTH_CONN`
`CONFIG_BLUETOOTH_L2CAP_TX_BUF_COUNT`	Number of L2CAP TX buffers
`CONFIG_BLUETOOTH_L2CAP_TX_MTU`	Maximum supported L2CAP MTU for L2CAP TX buffers
`CONFIG_BLUETOOTH_L2CAP_TX_USER_DATA_SIZE`	Maximum supported user data size for L2CAP TX buffers
`CONFIG_BLUETOOTH_PRIVACY`	Privacy Feature
`CONFIG_BLUETOOTH_RPA_TIMEOUT`	Resolvable Private Address timeout
`CONFIG_BLUETOOTH_SIGNING`	Data signing support
`CONFIG_BLUETOOTH_SMP_SC_ONLY`	Secure Connections Only Mode
`CONFIG_BLUETOOTH_USE_DEBUG_KEYS`	Enable Security Manager Debug Mode
`CONFIG_BLUETOOTH_L2CAP_DYNAMIC_CHANNEL`	L2CAP Dynamic Channel support
`CONFIG_BLUETOOTH_GATT_DYNAMIC_DB`	GATT dynamic database support
`CONFIG_BLUETOOTH_TINYCRYPT_ECC`	Use TinyCrypt library for ECDH
`CONFIG_BLUETOOTH_DEBUG`
`CONFIG_BLUETOOTH_DEBUG_NONE`	No debug log
`CONFIG_BLUETOOTH_DEBUG_LOG`	Normal printf-style to console
`CONFIG_BLUETOOTH_DEBUG_MONITOR`	Monitor protocol over UART
`CONFIG_BLUETOOTH_DEBUG_COLOR`	Use colored logs
`CONFIG_BLUETOOTH_MONITOR_ON_DEV_NAME`	Device Name of Bluetooth monitor logging UART
`CONFIG_BLUETOOTH_DEBUG_HCI_CORE`	Bluetooth HCI core debug
`CONFIG_BLUETOOTH_DEBUG_CONN`	Bluetooth connection debug
`CONFIG_BLUETOOTH_DEBUG_KEYS`	Bluetooth security keys debug
`CONFIG_BLUETOOTH_DEBUG_L2CAP`	Bluetooth L2CAP debug
`CONFIG_BLUETOOTH_DEBUG_SMP`	Bluetooth Security Manager Protocol (SMP) debug
`CONFIG_BLUETOOTH_SMP_SELFTEST`	Bluetooth SMP self tests executed on init
`CONFIG_BLUETOOTH_SMP_FORCE_BREDR`	Force Bluetooth SMP over BR/EDR
`CONFIG_BLUETOOTH_DEBUG_ATT`	Bluetooth Attribute Protocol (ATT) debug
`CONFIG_BLUETOOTH_DEBUG_RFCOMM`	Bluetooth RFCOMM debug
`CONFIG_BLUETOOTH_DEBUG_HFP_HF`	Bluetooth Hands Free Profile (HFP) debug
`CONFIG_BLUETOOTH_DEBUG_AVDTP`	Bluetooth AVDTP debug
`CONFIG_BLUETOOTH_DEBUG_A2DP`	Bluetooth A2DP debug
`CONFIG_BLUETOOTH_DEBUG_SDP`	Bluetooth Service Discovery Protocol (SDP) debug
`CONFIG_BLUETOOTH_BREDR`	Bluetooth BR/EDR support [EXPERIMENTAL]
`CONFIG_BLUETOOTH_RFCOMM`	Bluetooth RFCOMM protocol support [EXPERIMENTAL]
`CONFIG_BLUETOOTH_RFCOMM_L2CAP_MTU`	L2CAP MTU for RFCOMM frames
`CONFIG_BLUETOOTH_HFP_HF`	Bluetooth Handsfree profile HF Role support [EXPERIMENTAL]
`CONFIG_BLUETOOTH_AVDTP`	Bluetooth AVDTP protocol support [EXPERIMENTAL]
`CONFIG_BLUETOOTH_A2DP`	Bluetooth A2DP Profile [EXPERIMENTAL]
`CONFIG_BLUETOOTH_PAGE_TIMEOUT`	Bluetooth Page Timeout
`CONFIG_BLUETOOTH_CONTROLLER_RX_BUFFERS`	Number of Rx buffers
`CONFIG_BLUETOOTH_CONTROLLER_TX_BUFFERS`	Number of Tx buffers
`CONFIG_BLUETOOTH_CONTROLLER_TX_BUFFER_SIZE`	Tx buffer size
`CONFIG_BLUETOOTH_CONTROLLER_RX_PRIO_STACK_SIZE`
`CONFIG_BLUETOOTH_CONTROLLER_LE_PING`	LE Ping
`CONFIG_BLUETOOTH_CONTROLLER_DATA_LENGTH`	Data Length Update
`CONFIG_BLUETOOTH_CONTROLLER_DATA_LENGTH_MAX`	Maximum data length supported
`CONFIG_BLUETOOTH_CONTROLLER_FAST_ENC`	Fast Encryption Setup
`CONFIG_BLUETOOTH_CONTROLLER_CONN_RSSI`	Connection RSSI
`CONFIG_BLUETOOTH_CONTROLLER_ASSERT_HANDLER`	Bluetooth Controller Assertion Handler
`CONFIG_BLUETOOTH_CONTROLLER_PROFILE_ISR`	Profile radio ISR
`CONFIG_DISK_ACCESS`	Enable Disk Interface
`CONFIG_DISK_ACCESS_RAM`	RAM Disk
`CONFIG_DISK_ACCESS_FLASH`	Flash
`CONFIG_DISK_FLASH_DEV_NAME`	Flash device name to be used as storage backend
`CONFIG_DISK_FLASH_START`
`CONFIG_DISK_FLASH_MAX_RW_SIZE`
`CONFIG_DISK_FLASH_ERASE_ALIGNMENT`
`CONFIG_DISK_ERASE_BLOCK_SIZE`
`CONFIG_DISK_VOLUME_SIZE`
`CONFIG_NET_BUF`	Network buffer support
`CONFIG_NET_BUF_LOG`	Network buffer logging
`CONFIG_SYS_LOG_NET_BUF_LEVEL`	Network buffer Logging level
`CONFIG_NET_BUF_SIMPLE_LOG`	Network buffer memory debugging
`CONFIG_NETWORKING`	Link layer and IP networking support
`CONFIG_NET_L2_RAW_CHANNEL`
`CONFIG_NET_INIT_PRIO`
`CONFIG_NET_LOG`	Enable network stack logging and debugging
`CONFIG_SYS_LOG_NET_LEVEL`	Network Stack Logging level
`CONFIG_NET_LOG_GLOBAL`	Enable global network stack logging
`CONFIG_NET_DEBUG_CORE`	Debug core IP stack
`CONFIG_NET_DEBUG_IF`	Debug network interface code
`CONFIG_NET_DEBUG_UTILS`	Debug utility functions in IP stack
`CONFIG_NET_DEBUG_CONTEXT`	Debug network context allocation
`CONFIG_NET_DEBUG_NET_BUF`	Debug network buffer allocation
`CONFIG_NET_DEBUG_CONN`	Debug connection handling
`CONFIG_NET_DEBUG_ROUTE`	Debug route management
`CONFIG_NET_IPV6`	IPv6
`CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT`	Max number of unicast IPv6 addresses per network interface
`CONFIG_NET_IF_MCAST_IPV6_ADDR_COUNT`	Max number of multicast IPv6 addresses per network interface
`CONFIG_NET_IF_IPV6_PREFIX_COUNT`	Max number of IPv6 prefixes per network interface
`CONFIG_NET_INITIAL_HOP_LIMIT`	Initial hop limit for a connection
`CONFIG_NET_IPV6_MAX_NEIGHBORS`	How many IPv6 neighbors are supported
`CONFIG_NET_IPV6_ND`	Activate neighbor discovery
`CONFIG_NET_IPV6_DAD`	Activate duplicate address detection
`CONFIG_NET_IPV6_RA_RDNSS`	Support RA RDNSS option
`CONFIG_NET_6LO`	Enable 6lowpan IPv6 Compression library
`CONFIG_NET_6LO_CONTEXT`	Enable 6lowpan context based compression
`CONFIG_NET_MAX_6LO_CONTEXTS`	Number of supported 6CO (6lowpan contexts options)
`CONFIG_NET_DEBUG_6LO`	Enable 6lowpan debug
`CONFIG_NET_DEBUG_IPV6`	Debug core IPv6
`CONFIG_NET_DEBUG_ICMPV6`	Debug ICMPv6
`CONFIG_NET_DEBUG_IPV6_NBR_CACHE`	Debug IPv6 neighbour cache
`CONFIG_NET_IPV4`	IPv4
`CONFIG_NET_INITIAL_TTL`	Initial time to live for a connection
`CONFIG_NET_IF_UNICAST_IPV4_ADDR_COUNT`	Max number of unicast IPv4 addresses per network interface
`CONFIG_NET_IF_MCAST_IPV4_ADDR_COUNT`	Max number of multicast IPv4 addresses per network interface
`CONFIG_NET_DHCPV4`	Enable DHCPv4 client
`CONFIG_NET_DEBUG_IPV4`	Debug core IPv4
`CONFIG_NET_DEBUG_ICMPV4`	Debug ICMPv4
`CONFIG_NET_DEBUG_DHCPV4`	Debug DHCPv4 client
`CONFIG_NET_SHELL`	Enable network shell utilities
`CONFIG_NET_IP_ADDR_CHECK`	Check IP address validity before sending IP packet
`CONFIG_NET_MAX_ROUTERS`	How many routers are supported
`CONFIG_NET_ROUTE`
`CONFIG_NET_MAX_ROUTES`	Max number of routing entries stored.
`CONFIG_NET_MAX_NEXTHOPS`	Max number of next hop entries stored.
`CONFIG_NET_ROUTE_MCAST`
`CONFIG_NET_MAX_MCAST_ROUTES`	Max number of multicast routing entries stored.
`CONFIG_NET_TCP`	Enable TCP
`CONFIG_NET_DEBUG_TCP`	Debug TCP
`CONFIG_NET_TCP_TIME_WAIT`	Enable TCP TIME_WAIT timeouts
`CONFIG_NET_UDP`	Enable UDP
`CONFIG_NET_DEBUG_UDP`	Debug UDP
`CONFIG_NET_MAX_CONN`	How many network connections are supported
`CONFIG_NET_CONN_CACHE`	Cache network connections
`CONFIG_NET_MAX_CONTEXTS`	Number of network contexts to allocate
`CONFIG_NET_CONTEXT_SYNC_RECV`	Support synchronous functionality in net_context_recv() API
`CONFIG_NET_CONTEXT_CHECK`	Check options when calling various net_context functions
`CONFIG_NET_SLIP_TUN`	TUN SLIP driver
`CONFIG_NET_SLIP_TAP`	TAP SLIP driver
`CONFIG_NET_TRICKLE`	Enable Trickle library
`CONFIG_NET_DEBUG_TRICKLE`	Debug Trickle algorithm
`CONFIG_NET_NBUF_RX_COUNT`	How many network receives can be pending at the same time
`CONFIG_NET_NBUF_TX_COUNT`	How many network sends can be pending at the same time
`CONFIG_NET_NBUF_DATA_COUNT`	How many network data buffers are allocated
`CONFIG_NET_NBUF_DATA_SIZE`	Size of each network data fragment
`CONFIG_NET_NBUF_USER_DATA_SIZE`	Size of user_data reserved
`CONFIG_NET_TX_STACK_SIZE`	TX thread stack size
`CONFIG_NET_RX_STACK_SIZE`	RX thread stack size
`CONFIG_NET_RX_STACK_RPL`	RPL specific RX stack need
`CONFIG_NET_L2_DUMMY`	Enable dummy l2 layer
`CONFIG_NET_L2_ETHERNET`	Enable ethernet support
`CONFIG_NET_DEBUG_L2_ETHERNET`	Debug Ethernet L2 layer
`CONFIG_NET_L2_OFFLOAD_IP`	Offload IP stack [EXPERIMENTAL]
`CONFIG_NET_DEBUG_L2_OFFLOAD`	Debug IP Offload L2 layer
`CONFIG_NET_L2_BLUETOOTH`	Enable Bluetooth support
`CONFIG_NET_L2_BLUETOOTH_ZEP1656`	*Workaround to work with Linux.*
`CONFIG_NET_L2_BLUETOOTH_SEC_LEVEL`	Security level of Bluetooth Link
`CONFIG_NET_DEBUG_L2_BLUETOOTH`	Debug Bluetooth L2 layer
`CONFIG_NET_L2_BLUETOOTH_MGMT`	Enable Blueooth Network Management support
`CONFIG_NET_L2_BLUETOOTH_SHELL`	Enable Bluetooth shell module
`CONFIG_NET_L2_IEEE802154`	Enable IEEE 802.15.4 Radio
`CONFIG_NET_L2_IEEE802154_MGMT`
`CONFIG_NET_DEBUG_L2_IEEE802154`	Enable IEEE 802.15.4 stack debug messages
`CONFIG_NET_L2_IEEE802154_ACK_REPLY`	Enable IEEE 802.15.4 ACK reply logic
`CONFIG_NET_L2_IEEE802154_ORFD`	Support only an OVERLY Reduced Functionality Device
`CONFIG_NET_L2_IEEE802154_RFD`	Support Reduced Functionality Device level
`CONFIG_NET_L2_IEEE802154_SHELL`	Enable IEEE 802.15.4 shell module
`CONFIG_NET_L2_IEEE802154_ACK_SET`	Expose ACK request setting
`CONFIG_NET_L2_IEEE802154_ORFD_PAN_ID`	IEEE 802.15.4 fixed PAN ID
`CONFIG_NET_L2_IEEE802154_ORFD_CHANNEL`	IEEE 802.15.4 fixed channel
`CONFIG_NET_L2_IEEE802154_FRAGMENT`	Enable 802.15.4 fragmentation support
`CONFIG_NET_L2_IEEE802154_FRAGMENT_REASS_CACHE_SIZE`	IEEE 802.15.4 Reassembly cache size
`CONFIG_NET_L2_IEEE802154_REASSEMBLY_TIMEOUT`	IEEE 802.15.4 Reassembly timeout in seconds
`CONFIG_NET_DEBUG_L2_IEEE802154_FRAGMENT`	Enable debug support for IEEE 802.15.4 fragmentation
`CONFIG_NET_L2_IEEE802154_RADIO_TX_RETRIES`	Radio Transmission attempts
`CONFIG_NET_L2_IEEE802154_RADIO_CSMA_CA`	IEEE 802.15.4 CSMA-CA radio protocol
`CONFIG_NET_L2_IEEE802154_RADIO_ALOHA`	IEEE 802.15.4 Aloha radio protocol
`CONFIG_NET_L2_IEEE802154_RADIO_CSMA_CA_MAX_BO`	CSMA maximum backoffs
`CONFIG_NET_L2_IEEE802154_RADIO_CSMA_CA_MIN_BE`	CSMA MAC minimum backoff exponent
`CONFIG_NET_L2_IEEE802154_RADIO_CSMA_CA_MAX_BE`	CSMA MAC maximum backoff exponent
`CONFIG_NET_ARP`	Enable ARP
`CONFIG_NET_ARP_TABLE_SIZE`	Number of entries in ARP table.
`CONFIG_NET_DEBUG_ARP`	Debug IPv4 ARP
`CONFIG_NET_MGMT`	Network Management API
`CONFIG_NET_MGMT_EVENT`	Add support for runtime network event notifications
`CONFIG_NET_MGMT_EVENT_STACK_SIZE`	Stack size for the inner thread handling event callbacks
`CONFIG_NET_MGMT_EVENT_THREAD_PRIO`	Inner thread priority (use with care)
`CONFIG_NET_MGMT_EVENT_QUEUE_SIZE`	Size of event queue
`CONFIG_NET_DEBUG_MGMT_EVENT`	Enable debug output on Net MGMT event core
`CONFIG_NET_DEBUG_MGMT_EVENT_STACK`	Enable stack analysis output on Net MGMT event core
`CONFIG_NET_RPL`	Enable RPL (Ripple) support
`CONFIG_NET_RPL_MRHOF`	Minimum Rank with Hysteresis, RFC 6719
`CONFIG_NET_RPL_OF0`	OF Zero, RFC 6552
`CONFIG_NET_RPL_MC_NONE`	No routing metric
`CONFIG_NET_RPL_MC_EXT`	Estimated number of transmissions (ETX)
`CONFIG_NET_RPL_MC_ENERGY`	Energy based routing metric
`CONFIG_NET_RPL_MOP2`	Storing Mode of Operation with no multicast support
`CONFIG_NET_RPL_MOP3`	Storing Mode of Operation with multicast support
`CONFIG_NET_RPL_PROBING`	Enable RPL probing
`CONFIG_NET_RPL_MAX_INSTANCES`	Maximum number of RPL instances
`CONFIG_NET_RPL_MAX_DAG_PER_INSTANCE`	Maximum number of DAGs within an instance
`CONFIG_NET_RPL_DAO_SPECIFY_DAG`	Specify DAG when sending a DAO message.
`CONFIG_NET_RPL_DIO_INTERVAL_MIN`	DIO interval.
`CONFIG_NET_RPL_DIO_INTERVAL_DOUBLINGS`	Maximum amount of timer doublings.
`CONFIG_NET_RPL_DIO_REDUNDANCY`	DIO redundancy.
`CONFIG_NET_RPL_DEFAULT_LIFETIME_UNIT`	Default route lifetime unit.
`CONFIG_NET_RPL_DEFAULT_LIFETIME`	Default route lifetime.
`CONFIG_NET_RPL_MCAST_LIFETIME`	Multicast route lifetime.
`CONFIG_NET_RPL_MIN_HOP_RANK_INC`	Minimum hop rank increment
`CONFIG_NET_RPL_INIT_LINK_METRIC`	Initial link metric
`CONFIG_NET_RPL_DAO_TIMER`	DAO sending timer value
`CONFIG_NET_RPL_PREFERENCE`	DAG preference field default value
`CONFIG_NET_RPL_GROUNDED`	DAG grounded default value
`CONFIG_NET_RPL_DEFAULT_INSTANCE`	Default DAG instance id
`CONFIG_NET_RPL_INSERT_HBH_OPTION`	Add RPL Hop-by-hop ext header to sent UDP packets
`CONFIG_NET_RPL_DIS_SEND`	Send DIS periodically
`CONFIG_NET_RPL_DIS_INTERVAL`	Default DIS interval
`CONFIG_NET_DEBUG_RPL`	Debug RPL
`CONFIG_NET_STATISTICS`	Network statistics
`CONFIG_NET_STATISTICS_USER_API`	Expose statistics through NET MGMT API
`CONFIG_NET_STATISTICS_PERIODIC_OUTPUT`	Simple periodic output
`CONFIG_NET_STATISTICS_IPV4`	IPv4 statistics
`CONFIG_NET_STATISTICS_IPV6`	IPv6 statistics
`CONFIG_NET_STATISTICS_IPV6_ND`	IPv6 statistics
`CONFIG_NET_STATISTICS_ICMP`	ICMP statistics
`CONFIG_NET_STATISTICS_UDP`	UDP statistics
`CONFIG_NET_STATISTICS_TCP`	TCP statistics
`CONFIG_NET_STATISTICS_RPL`	RPL statistics
`CONFIG_NET_SAMPLES_IP_ADDRESSES`	Set IP addresses for sample applications
`CONFIG_NET_SAMPLES_MY_IPV6_ADDR`	My IPv6 address
`CONFIG_NET_SAMPLES_PEER_IPV6_ADDR`	Peer IPv6 address
`CONFIG_NET_SAMPLES_MY_IPV4_ADDR`	My IPv4 address
`CONFIG_NET_SAMPLES_PEER_IPV4_ADDR`	Peer IPv4 address
`CONFIG_ZOAP`	CoAP Support
`CONFIG_DNS_RESOLVER`	DNS resolver
`CONFIG_DNS_RESOLVER_ADDITIONAL_BUF_CTR`	Additional DNS buffers
`CONFIG_DNS_RESOLVER_ADDITIONAL_QUERIES`	Additional DNS queries
`CONFIG_MQTT_LIB`	MQTT Library Support
`CONFIG_MQTT_MSG_MAX_SIZE`	Max size of a MQTT message
`CONFIG_MQTT_ADDITIONAL_BUFFER_CTR`	Additional buffers available for the MQTT application
`CONFIG_MQTT_SUBSCRIBE_MAX_TOPICS`	Max number of topics to subscribe to
`CONFIG_HTTP_PARSER`	HTTP Parser support
`CONFIG_HTTP_PARSER_STRICT`	HTTP strict parsing
`CONFIG_SYS_LOG`	Enable Logging
`CONFIG_SYS_LOG_SHOW_TAGS`	Prepend level tags to logs
`CONFIG_SYS_LOG_SHOW_COLOR`	Use colored logs
`CONFIG_SYS_LOG_DEFAULT_LEVEL`	Default log level
`CONFIG_SYS_LOG_OVERRIDE_LEVEL`	Override lowest log level
`CONFIG_SYS_LOG_EXT_HOOK`	Use external hook function for logging
`CONFIG_MEM_SAFE`	Enable safe memory access
`CONFIG_MEM_SAFE_CHECK_BOUNDARIES`	Software validation of memory access within memory regions
`CONFIG_MEM_SAFE_NUM_EXTRA_REGIONS`	Number of safe memory access regions to be added at runtime
`CONFIG_DEBUG_INFO`	Enable system debugging information
`CONFIG_GDB_SERVER`	Enable GDB Server [EXPERIMENTAL]
`CONFIG_GDB_SERVER_MAX_SW_BP`	Maximum number of GDB Server Software breakpoints
`CONFIG_GDB_SERVER_INTERRUPT_DRIVEN`	Enable GDB interrupt mode
`CONFIG_GDB_REMOTE_SERIAL_EXT_NOTIF_PREFIX_STR`	Trigger string for remote serial ext. via notifi. packets
`CONFIG_GDB_SERVER_BOOTLOADER`	Enable the bootloader mode
`CONFIG_OPENOCD_SUPPORT`	OpenOCD support [EXPERIMENTAL]
`CONFIG_CONSOLE_SHELL`	Enable console input handler [ Experimental ]
`CONFIG_CONSOLE_SHELL_STACKSIZE`	Console handler shell stack size
`CONFIG_CONSOLE_SHELL_MAX_CMD_QUEUED`	Shell’s command queue size
`CONFIG_KERNEL_SHELL`	Enable kernel shell
`CONFIG_ASF`
`CONFIG_HAS_CMSIS`
`CONFIG_HAS_NORDIC_MDK`
`CONFIG_HAS_NORDIC_HAL`
`CONFIG_HAS_NORDIC_DRIVERS`
`CONFIG_HAS_MCUX`
`CONFIG_HAS_QMSI`
`CONFIG_QMSI`	QMSI driver support
`CONFIG_QMSI_BUILTIN`	Enable QMSI drivers through integrated sources
`CONFIG_QMSI_LIBRARY`	Enable QMSI drivers using external library
`CONFIG_QMSI_INSTALL_PATH`	QMSI install path
`CONFIG_SOC_WATCH`	Enable SoCWatch drivers and related instrumentation
`CONFIG_HAS_STM32CUBE`
`CONFIG_HAS_CC3200SDK`
`CONFIG_CC3200SDK`	TI CC3200 SDK support
`CONFIG_CC3200SDK_BUILTIN`	Enable building the CC3200 SDK files stored in the Zephyr tree
`CONFIG_CC3200SDK_ROM_DRIVERLIB`	Use the Peripheral Driver library functions in ROM
`CONFIG_TINYCRYPT`	Cryptography Support
`CONFIG_TINYCRYPT_CTR_PRNG`	PRNG in counter mode
`CONFIG_TINYCRYPT_SHA256`	SHA-256 Hash function support
`CONFIG_TINYCRYPT_SHA256_HMAC`	HMAC (via SHA256) message auth support
`CONFIG_TINYCRYPT_SHA256_HMAC_PRNG`	PRNG (via HMAC-SHA256) support
`CONFIG_TINYCRYPT_ECC_DH`	ECC_DH anonymous key agreement protocol
`CONFIG_TINYCRYPT_ECC_DSA`	ECC_DSA digital signature algorithm
`CONFIG_TINYCRYPT_AES`	AES-128 decrypt/encrypt
`CONFIG_TINYCRYPT_AES_CBC`	AES-128 block cipher
`CONFIG_TINYCRYPT_AES_CTR`	AES-128 counter mode
`CONFIG_TINYCRYPT_AES_CCM`	AES-128 CCM mode
`CONFIG_TINYCRYPT_AES_CMAC`	AES-128 CMAC mode
`CONFIG_MBEDTLS`	mbedTLS Support
`CONFIG_MBEDTLS_BUILTIN`	Enable mbedTLS integrated sources
`CONFIG_MBEDTLS_CFG_FILE`	mbed TLS configuration file
`CONFIG_MBEDTLS_TEST`	Compile internal self test functions
`CONFIG_MBEDTLS_LIBRARY`	Enable mbedTLS external library
`CONFIG_MBEDTLS_INSTALL_PATH`	mbedTLS install path
`CONFIG_FAT_FILESYSTEM_ELM`	ELM FAT File System
`CONFIG_HAS_SEGGER_RTT`	Segger RTT support
`CONFIG_ZTEST`	Zephyr testing framework
`CONFIG_ZTEST_STACKSIZE`	Test function thread stack size
`CONFIG_ZTEST_FAIL_FAST`	Abort on first failing test
`CONFIG_ZTEST_ASSERT_VERBOSE`	Assertion verbosity level
`CONFIG_ZTEST_MOCKING`	Mocking support functions
`CONFIG_ZTEST_PARAMETER_COUNT`	Count of parameters or return values reserved
`CONFIG_TEST_EXTRA_STACKSIZE`	Test function thread stack size
`CONFIG_ITCM_BASE_ADDRESS`
`CONFIG_ITCM_SIZE`
`CONFIG_DTCM_BASE_ADDRESS`
`CONFIG_DTCM_SIZE`
`CONFIG_RISCV_ROM_BASE_ADDR`
`CONFIG_RISCV_ROM_SIZE`
`CONFIG_RISCV_RAM_BASE_ADDR`
`CONFIG_RISCV_RAM_SIZE_MB`
`CONFIG_UART_NS16550_PORT_1_PCI`
`CONFIG_SOC_FAMILY_SAM`
`CONFIG_CC3200SDK_LIBRARY`
`CONFIG_FLASH_PAGE_SIZE`
`CONFIG_IEEE802154_CC2520_GPIO_0_NAME`
`CONFIG_IEEE802154_CC2520_GPIO_1_NAME`
`CONFIG_PINMUX_MPS2`