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CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR
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PLLM division factor needs to be set correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter. Allowed values: 2-63
Symbol: | CLOCK_STM32F4X_PLLM_DIV_FACTOR |
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Type: | int |
Value: | “2” |
User value: | (no user value) |
Visibility: | “n” |
Is choice item: | false |
Is defined: | true |
Is from env.: | false |
Is special: | false |
Ranges: |
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Prompts: |
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Default values: |
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Selects: | (no selects) |
Reverse (select-related) dependencies: | |
(no reverse dependencies) |
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Additional dependencies from enclosing menus and ifs: | |
SOC_SERIES_STM32F4X && CLOCK_CONTROL (value: “n”) |
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Locations: |
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