Zephyr flex icon blue

Complete flexibility & freedom of choice

- Open source & neutral governance
- Supports multiple hardware architectures
- Small footprint: scales from small Cortex-M devices to multi-core 64-bit CPUs

Zephyr cloud icon blue

Connect embedded devices securely to any cloud

- Multiple protocol options including BLE mesh and Thread
- Supporting industrial, automotive, smart city and smart home
- Cloud agnostic – Connect with transport layer security to any cloud

Zephyr safety icon blue

Develop products with safety built in

- Long-term support
- In-depth security development lifecycle
- Functional safety certification coming soon

Member Quotes

Find out how your organization can benefit from participating. Check out all the choices in our Membership section.

Over 200 boards supported

Zephyr supports more than 200 boards. Search our list for the hardware used in your application. This diversity of supported boards gives developers and product manufacturers multiple options to solve their embedded RTOS challenges with Zephyr. If your board is not supported out of the box, adding support for a new board is simple.

em board
Zephyr up squared board
Zephyr hexiwear k64 board
Zephyr stm32 board
More Boards

Our Members

Zephyr project members help shape the direction of the project and provide guidance to help all members of the community get the most out of Zephyr.

Platinum Members

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As of June 5, 2020

Top News & Events

Running and Testing TensorFlow Lite on Microcontrollers without hardware in Renode

This article originally appeared on the TensorFlow Lite blog. For more content like this, click here. Every day more and more software developers are […]

Zephyr RTOS and Nordic nRF52-DK: debugging, unit testing, project analysis

This tutorial originally ran on the PlatformIO docs website. You can find it here. For more content like this, click here. The goal […]

Zephyr Mini-Summit at Open Source Summit

July 2, 2020 | 2:00 – 3:30 pmRegistration Fees: Complimentary to all OSS+ELC NA Attendees Join us to learn more about the leading Open […]

Designing a RISC-V CPU in VHDL, Part 19: Adding Trace Dump Functionality

Written by Colin Riley, an Engineer and Writer at Domipheus Labs This part of a series of posts detailing the steps and learning […]